ZHCSDT9C June 2015  – June 2015

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Audio Characteristics (BTL)
    7. 7.7 Audio Characteristics (SE)
    8. 7.8 Audio Characteristics (PBTL)
    9. 7.9 Typical Characteristics, BTL Configuration
    10. 7.10Typical Characteristics, SE Configuration
    11. 7.11Typical Characteristics, PBTL Configuration
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagrams
    3. 9.3Feature Description
      1. 9.3.1Error Reporting
    4. 9.4Device Protection System
      1. 9.4.1Overload and Short Circuit Current Protection
      2. 9.4.2DC Speaker Protection
      3. 9.4.3Pin-to-Pin Short Circuit Protection (PPSC)
      4. 9.4.4Overtemperature Protection OTW and OTE
      5. 9.4.5Undervoltage Protection (UVP) and Power-on Reset (POR)
      6. 9.4.6Fault Handling
      7. 9.4.7Device Reset
  10. 10Application and Implementation
    1. 10.1Application Information
    2. 10.2Typical Applications
      1. 10.2.1Stereo BTL Application
        1. 10.2.1.1Design Requirements
        2. 10.2.1.2Detailed Design Procedures
          1. 10.2.1.2.1Decoupling Capacitor Recommendations
          2. 10.2.1.2.2PVDD Capacitor Recommendation
          3. 10.2.1.2.3PCB Material Recommendation
          4. 10.2.1.2.4Oscillator
      2. 10.2.2Application Curves
      3. 10.2.3Typical Application, Single Ended (1N) SE
        1. 10.2.3.1Design Requirements
        2. 10.2.3.2Detailed Design Procedures
        3. 10.2.3.3Application Curves
      4. 10.2.4Typical Application, Differential (2N) PBTL
        1. 10.2.4.1Design Requirements
        2. 10.2.4.2Detailed Design Procedures
        3. 10.2.4.3Application Curves
  11. 11Power Supply Recommendations
    1. 11.1Power Supplies
      1. 11.1.1VDD Supply
    2. 11.2Powering Up
    3. 11.3Powering Down
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Examples
      1. 12.2.1BTL Application Printed Circuit Board Layout Example
      2. 12.2.2SE Application Printed Circuit Board Layout Example
      3. 12.2.3PBTL Application Printed Circuit Board Layout Example
  13. 13器件和文档支持
    1. 13.1文档支持
    2. 13.2社区资源
    3. 13.3商标
    4. 13.4静电放电警告
    5. 13.5Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
订购信息

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

TPA3251D2 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1 mixed 1x BTL + 2x SE mode depending on output power conditions and system design.

10.2 Typical Applications

10.2.1 Stereo BTL Application

TPA3251D2 TypAppBTL.gifFigure 25. Typical Differential Input BTL Application

10.2.1.1 Design Requirements

For this design example, use the parameters in Table 6.

Table 6. Design Requirements, BTL Application

DESIGN PARAMETEREXAMPLE
Low Power (Pull-up) Supply3.3 V
Mid Power Supply 12 V12 V
High Power Supply12 - 36 V
Mode SelectionM2 = L
M1 = L
Analog InputsINPUT_A = ±3.9 V (peak, max)
INPUT_B = ± 3.9V (peak, max)
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Output FiltersInductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance3-8 Ω

10.2.1.2 Detailed Design Procedures

A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.

The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio volume decrease or intelligent power supply nominally operating at a low rail adjusting to a higher supply rail.

The device is inverting the audio signal from input to output.

The DVDD and AVDD pins are not recommended to be used as a voltage sources for external circuitry.

10.2.1.2.1 Decoupling Capacitor Recommendations

In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this application.

The voltage of the decoupling capacitors should be selected in accordance with good design practices. Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the selection of the 1μF that is placed on the power supply to each full-bridge. It must withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple current created by high power output. A minimum voltage rating of 50 V is required for use with a 36V power supply.

10.2.1.2.2 PVDD Capacitor Recommendation

The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These capacitors should be selected for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well designed system power supply, 1000 μF, 50 V supports most applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed switching.

10.2.1.2.3 PCB Material Recommendation

FR-4 Glass Epoxy material with 2 oz. (70 μm) copper is recommended for use with the TPA3251D2. The use of this material can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB trace inductance.

10.2.1.2.4 Oscillator

The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.

To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency can be changed from nominal to lower values. These values should be chosen such that the nominal and the lower value switching frequencies together results in the fewest cases of interference throughout the AM band. The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in master mode according to the description in the Recommended Operating Conditions table.

For slave mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to DVDD. This configures the OSC_I/O pins as inputs to be slaved from an external differential clock. In a master/slave system inter channel delay is automatically setup between the switching of the audio channels, which can be illustrated by no idle channels switching at the same time. This will not influence the audio output, but only the switch timing to minimize noise coupling between audio channels through the power supply to optimize audio performance and to get better operating conditions for the power supply. The inter channel delay will be setup for a slave device depending on the polarity of the OSC_I/O connection such that a slave mode 1 is selected by connecting the master device OSC_I/O to the slave 1 device OSC_I/O with same polarity (+ to + and - to -), and slave mode 2 is selected with the inverse polarity (+ to - and - to +).

10.2.2 Application Curves

Relevant performance plots for TPA3251D2 in BTL configuration are shown in Typical Characteristics, BTL Configuration

Table 7. Relevant Performance Plots, BTL Configuration

PLOT TITLEFIGURE NUMBER
Total Harmonic Distortion+Noise vs FrequencyFigure 1
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BWFigure 2
Total Harmonic Distortion + Noise vs Output PowerFigure 3
Output Power vs Supply Voltage, 10% THD+NFigure 4
Output Power vs Supply Voltage, 10% THD+NFigure 6
System Efficiency vs Output PowerFigure 6
System Power Loss vs Output PowerFigure 7
Output Power vs Case TemperatureFigure 8
Noise Amplitude vs FrequencyFigure 9

10.2.3 Typical Application, Single Ended (1N) SE

TPA3251D2 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1 mixed 1x BTL + 2x SE mode depending on output power conditions and system design.

TPA3251D2 TypAppSE.gifFigure 26. Typical Single Ended (1N) SE Application

10.2.3.1 Design Requirements

Refer to Stereo BTL Application for the Design Requirements.

Table 8. Design Requirements, SE Application

DESIGN PARAMETEREXAMPLE
Low Power (Pull-up) Supply3.3 V
Mid Power Supply 1 2V12 V
High Power Supply12 - 36 V
Mode SelectionM2 = H
M1 = H
Analog InputsINPUT_A = ±3.9 V (peak, max)
INPUT_B = ±3.9 V (peak, max)
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Output FiltersInductor-Capacitor Low Pass FIlter (15 µH + 680 nF)
Speaker Impedance2 - 8 Ω

10.2.3.2 Detailed Design Procedures

Refer to Stereo BTL Application for the Detailed Design Procedures.

10.2.3.3 Application Curves

Relevant performance plots for TPA3251D2 in PBTL configuration are shown in Typical Characteristics, SE Configuration

Table 9. Relevant Performance Plots, SE Configuration

PLOT TITLEFIGURE NUMBER
Total Harmonic Distortion+Noise vs Output PowerFigure 10
Total Harmonic Distortion+Noise vs FrequencyFigure 11
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BWFigure 12
Output Power vs Supply Voltage, 10% THD+NFigure 13
Output Power vs Supply Voltage, 1% THD+NFigure 14
Output Power vs Case TemperatureFigure 15

10.2.4 Typical Application, Differential (2N) PBTL

TPA3251D2 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1 mixed 1x BTL + 2x SE mode depending on output power conditions and system design.

TPA3251D2 TypAppPBTL.gifFigure 27. Typical Differential (2N) PBTL Application

10.2.4.1 Design Requirements

Refer to Stereo BTL Application for the Design Requirements.

Table 10. Design Requirements, PBTL Application

DESIGN PARAMETEREXAMPLE
Low Power (Pull-up) Supply3.3 V
Mid Power Supply 12 V12 V
High Power Supply12 - 36 V
Mode SelectionM2 = H
M1 = L
Analog InputsINPUT_A = ±3.9V (peak, max)
INPUT_B = ±3.9V (peak, max)
INPUT_C = Grounded
INPUT_D = Grounded
Output FiltersInductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance2 - 4 Ω

10.2.4.2 Detailed Design Procedures

Refer to Stereo BTL Application for the Detailed Design Procedures.

10.2.4.3 Application Curves

Relevant performance plots for TPA3251D2 in PBTL configuration are shown in Typical Characteristics, PBTL Configuration

Table 11. Relevant Performance Plots, PBTL Configuration

PLOT TITLEFIGURE NUMBER
Total Harmonic Distortion+Noise vs Output PowerFigure 16
Total Harmonic Distortion+Noise vs FrequencyFigure 17
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BWFigure 18
Output Power vs Supply Voltage, 10% THD+NFigure 19
Output Power vs Supply Voltage, 1% THD+NFigure 20
Output Power vs Case TemperatureFigure 21