产品详情

DSP type 1 C55x DSP (max) (MHz) 108, 144, 200 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
DSP type 1 C55x DSP (max) (MHz) 108, 144, 200 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PGE) 144 484 mm² 22 x 22 NFBGA (GBB) 179 144 mm² 12 x 12 NFBGA (ZAY) 179 144 mm² 12 x 12
  • High-Performance, Low-Power, Fixed-Point TMS320C55™ Digital Signal Processor
    • 9.26-, 6.95-, 5-ns Instruction Cycle Time
    • 108-, 144-, 200-MHz Clock Rate
    • One/Two Instruction(s) Executed per Cycle
    • Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
  • 64K × 16-Bit On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit
    • 64K Bytes of Single-Access RAM (SARAM) 8 Blocks of 4K × 16-Bit
  • 64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit)
  • 8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM)
  • 16-Bit External Parallel Bus Memory Supporting Either:
    • External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to:
      • Asynchronous Static RAM (SRAM)
      • Asynchronous EPROM
      • Synchronous DRAM (SDRAM)
    • 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Scan-Based Emulation Logic
  • On-Chip Peripherals
    • Two 20-Bit Timers
    • Watchdog Timer
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Phase-Locked Loop Clock Generator
    • Seven (LQFP) or Eight (BGA) General-Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF)
    • USB Full-Speed (12 Mbps) Slave Port Supporting Bulk, Interrupt and Isochronous Transfers
    • Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface
    • Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply
    • 4-Channel (BGA) or 2-Channel (LQFP) 10-Bit Successive Approximation A/D
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
    • 179-Terminal MicroStar BGA™ (Ball Grid Array) (GHH and ZHH Suffixes)
  • 1.2-V Core (108 MHz), 2.7-V - 3.6-V I/Os
  • 1.35-V Core (144 MHz), 2.7-V - 3.6-V I/Os
  • 1.6-V Core (200 MHz), 2.7-V - 3.6-V I/Os

C55x is a trademark of Texas Instruments.
TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

  • High-Performance, Low-Power, Fixed-Point TMS320C55™ Digital Signal Processor
    • 9.26-, 6.95-, 5-ns Instruction Cycle Time
    • 108-, 144-, 200-MHz Clock Rate
    • One/Two Instruction(s) Executed per Cycle
    • Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
  • 64K × 16-Bit On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit
    • 64K Bytes of Single-Access RAM (SARAM) 8 Blocks of 4K × 16-Bit
  • 64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit)
  • 8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM)
  • 16-Bit External Parallel Bus Memory Supporting Either:
    • External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to:
      • Asynchronous Static RAM (SRAM)
      • Asynchronous EPROM
      • Synchronous DRAM (SDRAM)
    • 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Scan-Based Emulation Logic
  • On-Chip Peripherals
    • Two 20-Bit Timers
    • Watchdog Timer
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Phase-Locked Loop Clock Generator
    • Seven (LQFP) or Eight (BGA) General-Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF)
    • USB Full-Speed (12 Mbps) Slave Port Supporting Bulk, Interrupt and Isochronous Transfers
    • Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface
    • Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply
    • 4-Channel (BGA) or 2-Channel (LQFP) 10-Bit Successive Approximation A/D
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
    • 179-Terminal MicroStar BGA™ (Ball Grid Array) (GHH and ZHH Suffixes)
  • 1.2-V Core (108 MHz), 2.7-V - 3.6-V I/Os
  • 1.35-V Core (144 MHz), 2.7-V - 3.6-V I/Os
  • 1.6-V Core (200 MHz), 2.7-V - 3.6-V I/Os

C55x is a trademark of Texas Instruments.
TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The TMS320VC5507 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 128K bytes of on-chip memory on 5507 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or more on-chip memory but less than 128K bytes of memory, and need to operate in standby mode for more than 60% to 70% of time. For the applications which require more than 128K bytes of on-chip memory but less than 256K bytes of on-chip memory, Texas Instruments (TI) offers the TMS320VC5509A device, which is based on the TMS320C55x DSP core.

The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs.

The 5507 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5507. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5507 is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry‘s largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX™, XDS51™. emulation device drivers, and evaluation modules. The 5507 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

The TMS320VC5507 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 128K bytes of on-chip memory on 5507 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or more on-chip memory but less than 128K bytes of memory, and need to operate in standby mode for more than 60% to 70% of time. For the applications which require more than 128K bytes of on-chip memory but less than 256K bytes of on-chip memory, Texas Instruments (TI) offers the TMS320VC5509A device, which is based on the TMS320C55x DSP core.

The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs.

The 5507 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5507. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5507 is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry‘s largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX™, XDS51™. emulation device drivers, and evaluation modules. The 5507 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

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类型 标题 下载最新的英语版本 日期
* 数据表 TMS320VC5507 Fixed-Point Digital Signal Processor 数据表 (Rev. J) 2008年 1月 22日
* 勘误表 TMS320VC5507 Digital Signal Processor Silicon Errata (Rev. C) 2008年 4月 9日
* 勘误表 TMS320VC5503/VC5506/VC5507/VC5509A Microstar BGA Discontinued and Redesigned 2022年 5月 10日
应用手册 高速接口布局指南 (Rev. J) PDF | HTML 英语版 (Rev.J) PDF | HTML 2023年 3月 23日
用户指南 TMS320VC5503/5507/5509 DSP Host Port Interface (HPI) Reference Guide (Rev. C) 2009年 6月 11日
应用手册 Board and System Design Considerations for the TMS320VC5503/06/07/09A DSPs 2008年 11月 19日
应用手册 Using the TMS320VC5506/C5507/C5509/C5509A USB Bootloader (Rev. C) 2008年 10月 1日
应用手册 Disabling the Internal Oscillator on the TMSVC5503/C5506/C5507/C5509/C5509A DSP (Rev. D) 2008年 9月 9日
应用手册 Using the USB APLL on the TMS320VC5506/C5507/C5509A (Rev. B) 2008年 9月 9日
应用手册 TMS320VC5503/VC5506/VC5507/C5509A Power Consumption Summary (Rev. C) 2008年 9月 5日
应用手册 Using the TMS320VC5503/C5506/C5507/C5509/C5509A Bootloader (Rev. F) 2008年 9月 5日
用户指南 TMS320VC5503/5507/5509/5510 Direct Memory Access(DMA) Controller Reference Guide (Rev. E) 2007年 1月 9日
用户指南 TMS320VC5503/5507/5509/5510 DSP Timers Reference Guide (Rev. C) 2006年 4月 11日
用户指南 TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module RG (Rev. D) 2005年 10月 17日
用户指南 TMS320VC5501/5502/5503/5507/5509/5510 DSP (McBSP) Reference Guide (Rev. E) 2005年 4月 14日
应用手册 Recommended Power Solutions For TMS320C5509A/07/03 2005年 3月 28日
用户指南 TMS320C55x DSP CPU Programmer's Reference Supplement (Rev. G) 2005年 2月 24日
用户指南 TMS320VC5503/5507/5509 DSP Real-Time Clock (RTC) Reference Guide (Rev. B) 2004年 6月 25日
应用手册 TMS320VC5507 Hardware Designer's Resource Guide 2004年 6月 25日
用户指南 TMS320VC5507/5509 DSP Analog-to-Digital Converter (ADC) Reference Guide (Rev. B) 2004年 6月 25日
用户指南 TMS320VC5507/5509 DSP Universal Serial Bus (USB) Module Reference Guide (Rev. A) 2004年 6月 25日
用户指南 TMS320VC5503/5507/5509 DSP External Memory Interface (EMIF) Reference Guide (Rev. A) 2004年 6月 4日
用户指南 TMS320C55x DSP CPU Reference Guide (Rev. F) 2004年 2月 25日
用户指南 TMS320C55x DSP Mnemonic Instruction Set Reference Guide (Rev. G) 2002年 10月 11日

设计和开发

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调试探针

TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针(仿真器)。与低成本的 XDS110 和高性能的 XDS560v2 相比,XDS200 在低成本和高性能之间实现了平衡;并在单个仓体中支持广泛的标准(IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的内核跟踪,则需要使用 XDS560v2 PRO TRACE

XDS200 通过 TI 20 引脚连接器(带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 (...)

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调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的产品,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意,它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪,需要 XDS560v2 PRO TRACE

XDS560v2 通过 MIPI HSPT 60 引脚连接器(带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器)连接到目标板,并通过 USB2.0 高速 (480Mbps) (...)

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调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

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驱动程序或库

SPRC100 — TMS320C55x DSP 库

The DSP Library (DSPLIB) is a collection of high-level optimized DSP function modules for the C55x DSP platform. This source-code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions that have been ported to C55x DSPs. The (...)
用户指南: PDF
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
IDE、配置、编译器或调试器

CCSTUDIO Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

支持的产品和硬件

支持的产品和硬件

此设计资源支持这些类别中的大部分产品。

查看产品详情页,验证是否能提供支持。

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软件编解码器

C55XCODECSAUD 用于 C55x 的音频编解码器 - 软件和文档

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
OMAP5912 应用处理器
数字信号处理器 (DSP)
SM320VC5507-EP 低功耗 C5507 定点 DSP(增强型产品) TMS320VC5501 低功耗 C55x 定点 DSP- 高达 300MHz TMS320VC5502 定点数字信号处理器 TMS320VC5503 低功耗 C55x 定点 DSP- 高达 200MHz TMS320VC5505 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320VC5506 低功耗 C55x 定点 DSP - 108MHz TMS320VC5507 定点数字信号处理器 TMS320VC5509A 定点数字信号处理器 TMS320VC5510A 定点数字信号处理器
下载选项
软件编解码器

C55XCODECSPCH 用于 C55x 的语音编解码器 - 软件和文档

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
OMAP5912 应用处理器
数字信号处理器 (DSP)
SM320VC5507-EP 低功耗 C5507 定点 DSP(增强型产品) TMS320VC5501 低功耗 C55x 定点 DSP- 高达 300MHz TMS320VC5502 定点数字信号处理器 TMS320VC5503 低功耗 C55x 定点 DSP- 高达 200MHz TMS320VC5505 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320VC5506 低功耗 C55x 定点 DSP - 108MHz TMS320VC5507 定点数字信号处理器 TMS320VC5509A 定点数字信号处理器 TMS320VC5510A 定点数字信号处理器
下载选项
仿真模型

VC5507 GHH BSDL Model

SPRM211.ZIP (6 KB) - BSDL Model
仿真模型

VC5507 GHH IBIS Model

SPRM478.ZIP (88 KB) - IBIS Model
仿真模型

VC5507 PGE BSDL Model

SPRM210.ZIP (6 KB) - BSDL Model
仿真模型

VC5507 PGE IBIS Model

SPRM479.ZIP (87 KB) - IBIS Model
设计工具

PROCESSORS-3P-SEARCH — 基于 Arm® 的 MPU、基于 Arm 的 MCU 和 DSP 第三方搜索工具

TI 已与多家公司合作,提供各种使用 TI 处理器的软件、工具和 SOM,从而加快您的量产速度。下载此搜索工具,快速浏览我们的第三方解决方案,并寻找合适的第三方来满足您的需求。此处所列的软件、工具和模块由独立的第三方生产和管理,而非德州仪器 (TI)。

搜索工具按产品类型划分为以下类别:

  • 工具包括 IDE/编译器、调试和跟踪、仿真和建模软件以及闪存编程器。
  • 操作系统包括 TI 处理器支持的操作系统。
  • 应用软件是指应用特定的软件,包括在 TI 处理器上运行的中间件和库。
  • SoM 是模块上系统解决方案
封装 引脚 下载
LQFP (PGE) 144 查看选项
NFBGA (GBB) 179 查看选项
NFBGA (ZAY) 179 查看选项

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包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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