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DSP type 1 C55x DSP (max) (MHz) 200, 300 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
DSP type 1 C55x DSP (max) (MHz) 200, 300 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PGF) 176 676 mm² 26 x 26 NFBGA (GBE) 201 225 mm² 15 x 15 NFBGA (ZAV) 201 225 mm² 15 x 15
  • High-Performance, Low-Power, Fixed-Point TMS320C55x™ Digital Signal Processor (DSP)
    • 3.33-/5-ns Instruction Cycle Time
    • 300-/200-MHz Clock Rate
    • 16K-Byte Instruction Cache (I-Cache)
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses
  • Instruction Cache (16K Bytes)
  • 32K x 16-Bit On-Chip RAM That is Composed of Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)
  • 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)
  • 8M × 16-Bit Maximum Addressable External Memory Space
  • 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:
    • Asynchronous Static RAM (SRAM)
    • Asynchronous EPROM
    • Synchronous DRAM (SDRAM)
    • Synchronous Burst RAM (SBRAM)
  • Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Peripherals
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Analog Phase-Locked Loop (APLL) Clock Generator
    • General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF)
    • 8-Bit/16-Bit Parallel Host-Port Interface (HPI)
    • Four Timers
      • Two 64-Bit General-Purpose Timers
      • 64-Bit Programmable Watchdog Timer
      • 64-Bit DSP/BIOS™ Counter
    • Inter-Integrated Circuit (I2C) Interface
    • Universal Asynchronous Receiver/Transmitter (UART)
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix)
    • 201-Terminal MicroStar BGA™ (Ball Grid Array) (GZZ and ZZZ Suffixes)
  • 3.3-V I/O Supply Voltage
  • 1.26-V Core Supply Voltage

(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

NOTE: This document is designed to be used in conjunction with the TMS320C55x DSP CPU Reference Guide (literature number SPRU371).

TMS320C55x, DSP/BIOS, MicroStar BGA, C55x, eXpressDSP, Code Composer Studio, RTDX, XDS510, TMS320C54x, C54x, TMS320, TMS320C5000 are trademarks of Texas Instruments.
I2C bus is a trademark of Koninklijke Philips Electronics N.V.
All trademarks are the property of their respective owners.

  • High-Performance, Low-Power, Fixed-Point TMS320C55x™ Digital Signal Processor (DSP)
    • 3.33-/5-ns Instruction Cycle Time
    • 300-/200-MHz Clock Rate
    • 16K-Byte Instruction Cache (I-Cache)
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses
  • Instruction Cache (16K Bytes)
  • 32K x 16-Bit On-Chip RAM That is Composed of Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)
  • 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)
  • 8M × 16-Bit Maximum Addressable External Memory Space
  • 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:
    • Asynchronous Static RAM (SRAM)
    • Asynchronous EPROM
    • Synchronous DRAM (SDRAM)
    • Synchronous Burst RAM (SBRAM)
  • Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Peripherals
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Analog Phase-Locked Loop (APLL) Clock Generator
    • General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF)
    • 8-Bit/16-Bit Parallel Host-Port Interface (HPI)
    • Four Timers
      • Two 64-Bit General-Purpose Timers
      • 64-Bit Programmable Watchdog Timer
      • 64-Bit DSP/BIOS™ Counter
    • Inter-Integrated Circuit (I2C) Interface
    • Universal Asynchronous Receiver/Transmitter (UART)
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix)
    • 201-Terminal MicroStar BGA™ (Ball Grid Array) (GZZ and ZZZ Suffixes)
  • 3.3-V I/O Supply Voltage
  • 1.26-V Core Supply Voltage

(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

NOTE: This document is designed to be used in conjunction with the TMS320C55x DSP CPU Reference Guide (literature number SPRU371).

TMS320C55x, DSP/BIOS, MicroStar BGA, C55x, eXpressDSP, Code Composer Studio, RTDX, XDS510, TMS320C54x, C54x, TMS320, TMS320C5000 are trademarks of Texas Instruments.
I2C bus is a trademark of Koninklijke Philips Electronics N.V.
All trademarks are the property of their respective owners.

The TMS320VC5502 (5502) fixed-point digital signal processor (DSP) is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity.

The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 5502 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is a 8-/16-bit parallel interface used to provide host processor access to 32K words of internal memory on the 5502. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL) clock generation are also included.

The 5502 is supported by the industry's award-winning eXpress DSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments. algorithm standard, and the industry's largest third-party network. The Code Composer Studio™ IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5502 is also supported by the C55x™ DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

The TMS320VC5502 (5502) fixed-point digital signal processor (DSP) is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity.

The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 5502 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is a 8-/16-bit parallel interface used to provide host processor access to 32K words of internal memory on the 5502. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL) clock generation are also included.

The 5502 is supported by the industry's award-winning eXpress DSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments. algorithm standard, and the industry's largest third-party network. The Code Composer Studio™ IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5502 is also supported by the C55x™ DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

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类型 标题 下载最新的英语版本 日期
* 数据表 TMS320VC5502 Fixed-Point Digital Signal Processor 数据表 (Rev. K) 2008年 11月 20日
* 勘误表 TMS320VC5501/VC5502 MicroStar BGA Discontinued and Redesigned 2020年 5月 21日
* 勘误表 TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata (Rev. L) 2007年 6月 22日
应用手册 TMS320VC5502 to TMS320C5517 Hardware Migration Guide 2018年 7月 31日
应用手册 TMS320VC5501, TMS320VC5502 Power Consumption Summary (Rev. A) 2016年 12月 13日
用户指南 TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K) 2011年 12月 15日
用户指南 TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module RG (Rev. D) 2005年 10月 17日
用户指南 TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide (Rev. F) 2005年 8月 22日
用户指南 TMS320VC5501/5502/5503/5507/5509/5510 DSP (McBSP) Reference Guide (Rev. E) 2005年 4月 14日
用户指南 TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (Rev. G) 2005年 3月 24日
用户指南 TMS320C55x DSP CPU Programmer's Reference Supplement (Rev. G) 2005年 2月 24日
用户指南 TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (Rev. D) 2004年 11月 12日
应用手册 Using the TMS320VC5501/5502 Bootloader (Rev. C) 2004年 10月 19日
用户指南 TMS320C55x Chip Support Library API Reference Guide (Rev. J) 2004年 9月 15日
应用手册 TMS320VC5502 Hardware Designer's Resource Guide 2004年 7月 22日
应用手册 Achieving Efficient Memory System Performance w/ I-Cache on the TMS320VC5501/02 (Rev. A) 2004年 6月 24日
用户指南 TMS320VC5501/5502 DSP Instruction Cache Reference Guide (Rev. C) 2004年 6月 16日
用户指南 TMS320VC5501/5502 DSP Timers Reference Guide (Rev. B) 2004年 4月 19日
用户指南 TMS320C55x DSP CPU Reference Guide (Rev. F) 2004年 2月 25日
用户指南 TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) RG (Rev. B) 2003年 12月 30日
应用手册 Migrating from TMS320VC5402A to TMS320VC5502 2003年 11月 21日
应用手册 Migrating from TMS320VC5510 to TMS320VC5502 2003年 2月 28日
用户指南 TMS320C55x DSP Mnemonic Instruction Set Reference Guide (Rev. G) 2002年 10月 11日

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TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针(仿真器)。与低成本的 XDS110 和高性能的 XDS560v2 相比,XDS200 在低成本和高性能之间实现了平衡;并在单个仓体中支持广泛的标准(IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的内核跟踪,则需要使用 XDS560v2 PRO TRACE

XDS200 通过 TI 20 引脚连接器(带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 (...)

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所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪,需要 XDS560v2 PRO TRACE

XDS560v2 通过 MIPI HSPT 60 引脚连接器(带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器)连接到目标板,并通过 USB2.0 高速 (480Mbps) (...)

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调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

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驱动程序或库

SPRC100 — TMS320C55x DSP 库

The DSP Library (DSPLIB) is a collection of high-level optimized DSP function modules for the C55x DSP platform. This source-code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions that have been ported to C55x DSPs. The (...)
用户指南: PDF
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
IDE、配置、编译器或调试器

CCSTUDIO Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

支持的产品和硬件

支持的产品和硬件

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软件编解码器

C55XCODECSAUD 用于 C55x 的音频编解码器 - 软件和文档

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
OMAP5912 应用处理器
数字信号处理器 (DSP)
SM320VC5507-EP 低功耗 C5507 定点 DSP(增强型产品) TMS320VC5501 低功耗 C55x 定点 DSP- 高达 300MHz TMS320VC5502 定点数字信号处理器 TMS320VC5503 低功耗 C55x 定点 DSP- 高达 200MHz TMS320VC5505 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320VC5506 低功耗 C55x 定点 DSP - 108MHz TMS320VC5507 定点数字信号处理器 TMS320VC5509A 定点数字信号处理器 TMS320VC5510A 定点数字信号处理器
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软件编解码器

C55XCODECSPCH 用于 C55x 的语音编解码器 - 软件和文档

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
OMAP5912 应用处理器
数字信号处理器 (DSP)
SM320VC5507-EP 低功耗 C5507 定点 DSP(增强型产品) TMS320VC5501 低功耗 C55x 定点 DSP- 高达 300MHz TMS320VC5502 定点数字信号处理器 TMS320VC5503 低功耗 C55x 定点 DSP- 高达 200MHz TMS320VC5505 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320VC5506 低功耗 C55x 定点 DSP - 108MHz TMS320VC5507 定点数字信号处理器 TMS320VC5509A 定点数字信号处理器 TMS320VC5510A 定点数字信号处理器
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仿真模型

C5502 GGW BSDL Model (Rev. A)

SPRM128A.ZIP (6 KB) - BSDL Model
仿真模型

C5502 GGW IBIS Model (Rev. A)

SPRM130A.ZIP (106 KB) - IBIS Model
仿真模型

C5502 GZZ BSDL Model (Rev. A)

SPRM136A.ZIP (6 KB) - BSDL Model
仿真模型

C5502 GZZ IBIS Model (Rev. A)

SPRM135A.ZIP (106 KB) - IBIS Model
仿真模型

C5502 PGF BSDL Model (Rev. A)

SPRM127A.ZIP (6 KB) - BSDL Model
仿真模型

C5502 PGF IBIS Model (Rev. A)

SPRM129A.ZIP (106 KB) - IBIS Model
设计工具

PROCESSORS-3P-SEARCH — 基于 Arm® 的 MPU、基于 Arm 的 MCU 和 DSP 第三方搜索工具

TI 已与多家公司合作,提供各种使用 TI 处理器的软件、工具和 SOM,从而加快您的量产速度。下载此搜索工具,快速浏览我们的第三方解决方案,并寻找合适的第三方来满足您的需求。此处所列的软件、工具和模块由独立的第三方生产和管理,而非德州仪器 (TI)。

搜索工具按产品类型划分为以下类别:

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  • 操作系统包括 TI 处理器支持的操作系统。
  • 应用软件是指应用特定的软件,包括在 TI 处理器上运行的中间件和库。
  • SoM 是模块上系统解决方案
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  • 器件标识
  • 引脚镀层/焊球材料
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