SPRS902D October 2014  – July 2017 TMS320F28075


  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Signal Descriptions
    3. 4.3Pins With Internal Pullup and Pulldown
    4. 4.4Pin Multiplexing
      1. 4.4.1GPIO Muxed Pins
      2. 4.4.2Input X-BAR
      3. 4.4.3Output X-BAR and ePWM X-BAR
      4. 4.4.4USB Pin Muxing
      5. 4.4.5High-Speed SPI Pin Muxing
    5. 4.5Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings - Commercial
    3. 5.3 ESD Ratings - Automotive
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Consumption Summary
      1. 5.5.1Current Consumption Graphs
      2. 5.5.2Reducing Current Consumption
    6. 5.6 Electrical Characteristics
    7. 5.7 Thermal Resistance Characteristics
      1. 5.7.1PTP Package
      2. 5.7.2PZP Package
    8. 5.8 System
      1. 5.8.1Power Management
        1. 1.2-V VREG
        2. Sequencing
      2. 5.8.2Reset Timing
        1. Sources
        2. Electrical Data and Timing
      3. 5.8.3Clock Specifications
        1. Sources
        2. Frequencies, Requirements, and Characteristics
          1. Clock Frequency and Timing Requirements, PLL Lock Times
          2. Clock Frequencies
          3. Clock Frequency and Switching Characteristics
        3. Clocks and PLLs
        4. Oscillator
        5. Oscillators
      4. 5.8.4Flash Parameters
      5. 5.8.5Emulation/JTAG
        1. Electrical Data and Timing
      6. 5.8.6GPIO Electrical Data and Timing
        1. GPIO - Output Timing
        2. GPIO - Input Timing
        3. Window Width for Input Signals
      7. 5.8.7Interrupts
        1. Interrupt (XINT) Electrical Data and Timing
      8. 5.8.8Low-Power Modes
        1. Low-Power Modes
        2. Low-Power Modes
        3. Mode Wakeup Timing
      9. 5.8.9External Memory Interface (EMIF)
        1. Memory Support
        2. DRAM Support
        3. Electrical Data and Timing
          1. RAM
          2. RAM
    9. 5.9 Analog Peripherals
      1. 5.9.1Analog-to-Digital Converter (ADC)
        1. Electrical Data and Timing
          1. Input Model
          2. Timing Diagrams
        2. Sensor Electrical Data and Timing
      2. 5.9.2Comparator Subsystem (CMPSS)
        1. Electrical Data and Timing
      3. 5.9.3Buffered Digital-to-Analog Converter (DAC)
        1. DAC Electrical Data and Timing
    10. 5.10Control Peripherals
      1. 5.10.1Enhanced Capture (eCAP)
        1. Electrical Data and Timing
      2. 5.10.2Enhanced Pulse Width Modulator (ePWM)
        1. Peripherals Synchronization
        2. Electrical Data and Timing
          1. Input Timing
        3. ADC Start-of-Conversion Electrical Data and Timing
      3. 5.10.3Enhanced Quadrature Encoder Pulse (eQEP)
        1. Electrical Data and Timing
      4. 5.10.4High-Resolution Pulse Width Modulator (HRPWM)
        1. Electrical Data and Timing
      5. 5.10.5Sigma-Delta Filter Module (SDFM)
        1. Electrical Data and Timing
    11. 5.11Communications Peripherals
      1. 5.11.1Controller Area Network (CAN)
      2. 5.11.2Inter-Integrated Circuit (I2C)
        1. Electrical Data and Timing
      3. 5.11.3Multichannel Buffered Serial Port (McBSP)
        1. Electrical Data and Timing
          1. Transmit and Receive Timing
          2. as SPI Master or Slave Timing
      4. 5.11.4Serial Communications Interface (SCI)
      5. 5.11.5Serial Peripheral Interface (SPI)
        1. Electrical Data and Timing
          1. Master Mode Timings
          2. Slave Mode Timings
          3. Master Mode Timings
          4. Slave Mode Timings
      6. 5.11.6Universal Serial Bus (USB) Controller
        1. Electrical Data and Timing
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Memory
      1. 6.3.1C28x Memory Map
      2. 6.3.2Flash Memory Map
      3. 6.3.3EMIF Chip Select Memory Map
      4. 6.3.4Peripheral Registers Memory Map
      5. 6.3.5Memory Types
        1. RAM (Mx and Dx RAM)
        2. Shared RAM (LSx RAM)
        3. Shared RAM (GSx RAM)
        4. Message RAM (CLA MSGRAM)
    4. 6.4 Identification
    5. 6.5 Bus Architecture - Peripheral Connectivity
    6. 6.6 C28x Processor
      1. 6.6.1Floating-Point Unit
      2. 6.6.2Trigonometric Math Unit
    7. 6.7 Control Law Accelerator
    8. 6.8 Direct Memory Access
    9. 6.9 Boot ROM and Peripheral Booting
      1. 6.9.1EMU Boot or Emulation Boot
      2. 6.9.2WAIT Boot Mode
      3. 6.9.3Get Mode
      4. 6.9.4Peripheral Pins Used by Bootloaders
    10. 6.10Dual Code Security Module
    11. 6.11Timers
    12. 6.12Nonmaskable Interrupt With Watchdog Timer (NMIWD)
    13. 6.13Watchdog
    14. 6.14Configurable Logic Block (CLB)
  7. 7Applications, Implementation, and Layout
    1. 7.1TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1Device and Development Support Tool Nomenclature
    2. 8.2Tools and Software
    3. 8.3Documentation Support
    4. 8.4Related Links
    5. 8.5Community Resources
    6. 8.6Trademarks
    7. 8.7Electrostatic Discharge Caution
    8. 8.8Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1Packaging Information

Device Overview


  • TMS320C28x 32-Bit CPU
    • 120 MHz
    • IEEE 754 Single-Precision Floating-Point Unit (FPU)
    • Trigonometric Math Unit (TMU)
  • Programmable Control Law Accelerator (CLA)
    • 120 MHz
    • IEEE 754 Single-Precision Floating-Point Instructions
    • Executes Code Independently of Main CPU
  • On-Chip Memory
    • 512KB (256KW) of Flash (ECC-Protected)
    • 100KB (50KW) of RAM (ECC-Protected or Parity-Protected)
    • Dual-Zone Security Supporting Third-Party Development
  • Clock and System Control
    • Two Internal Zero-Pin 10-MHz Oscillators
    • On-Chip Crystal Oscillator
    • Windowed Watchdog Timer Module
    • Missing Clock Detection Circuitry
  • 3.3-V I/O With Available Internal Voltage Regulator for 1.2-V Core Supply
  • System Peripherals
    • External Memory Interface (EMIF) With ASRAM and SDRAM Support
    • 6-Channel Direct Memory Access (DMA) Controller
    • Up to 97 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins With Input Filtering
    • Expanded Peripheral Interrupt Controller (ePIE)
    • Multiple Low-Power Mode (LPM) Support With External Wakeup
  • Communications Peripherals
    • USB 2.0 (MAC + PHY)
    • Two Controller Area Network (CAN) Modules (Pin-Bootable)
    • Three High-Speed (up to 30-MHz) SPI Ports
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • Four Serial Communications Interfaces (SCI/UART) (Pin-Bootable)
    • Two I2C Interfaces (Pin-Bootable)
  • Analog Subsystem
    • Up to Three Analog-to-Digital Converters (ADCs)
      • 12-Bit Mode
        • 3.1 MSPS Each (up to 9.3-MSPS System Throughput)
        • Single-Ended Inputs
        • Up to 17 External Channels
      • Single Sample-and-Hold (S/H) on Each ADC
      • Hardware-Integrated Post-Processing of ADC Conversions
        • Saturating Offset Calibration
        • Error From Setpoint Calculation
        • High, Low, and Zero-Crossing Compare, With Interrupt Capability
        • Trigger-to-Sample Delay Capture
    • Eight Windowed Comparators With 12-Bit Digital-to-Analog Converter (DAC) References
    • Three 12-Bit Buffered DAC Outputs
  • Enhanced Control Peripherals
    • 24 PWM Channels With Enhanced Features
    • 16 High-Resolution Pulse Width Modulator (HRPWM) Channels
      • High Resolution on Both A and B Channels of 8 PWM Modules
      • Dead-Band Support (on Both Standard and High Resolution)
    • Six Enhanced Capture (eCAP) Modules
    • Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
    • Up to Eight Sigma-Delta Filter Module (SDFM) Input Channels, 2 Parallel Filters per Channel
      • Standard SDFM Data Filtering
      • Comparator Filter for Fast Action for Out of Range
  • Package Options:
    • 176-Pin PowerPAD™ Thermally Enhanced Low-Profile Quad Flatpack (HLQFP) [PTP Suffix]
    • 100-Pin PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP) [PZP Suffix]
  • Temperature Options:
    • T: –40ºC to 105ºC Junction
    • S: –40ºC to 125ºC Junction
    • Q: –40ºC to 125ºC Free-Air
      (AEC Q100 Qualification for Automotive Applications)


The TMS320F2807x microcontroller platform is part of the Piccolo™ family and is suited for advanced closed-loop control applications such as industrial drives and servo motor control; solar inverters and converters; digital power; transportation; and power line communications. Complete development packages for digital power and industrial drives are available as part of the powerSUITE and DesignDRIVE initiatives.

The F2807x is a 32-bit floating-point microcontroller based on TI’s industry-leading C28x core. This core is boosted by the trigonometric hardware accelerator which improves performance of trigonometric-based algorithms with CPU instructions such as sine, cosine, and arctangent functions, which are common in torque-loop and position calculations.

The F2807x microcontroller family features a CLA real-time control coprocessor. The CLA is an independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can effectively double the computational performance of a real-time control system. By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and diagnostics.

The F2807x device supports up to 512KB (256KW) of ECC-protected onboard flash memory and up to 100KB (50KW) of SRAM with parity. Two independent security zones are also available for 128-bit code protection of the main C28x.

The analog subsystem boasts up to three 12-bit ADCs, which enable simultaneous management of three independent power phases, and up to eight windowed comparator subsystems (CMPSSs), allowing very fast, direct trip of the PWMs in overvoltage or overcurrent conditions. In addition, the device has three 12-bit DACs, and precision control peripherals such as enhanced pulse width modulators (ePWMs) with fault protection, eQEP peripherals, and eCAP units.

Connectivity peripherals such as dual Controller Area Network (CAN) modules (ISO 11898-1/CAN 2.0B-compliant) and a USB 2.0 port with MAC and full-speed PHY let users add universal serial bus (USB) connectivity to their application.

Device Information(1)

TMS320F28076PTPHLQFP (176)24.0 mm × 24.0 mm
TMS320F28075PTPHLQFP (176)24.0 mm × 24.0 mm
TMS320F28076PZPHTQFP (100)14.0 mm × 14.0 mm
TMS320F28075PZPHTQFP (100)14.0 mm × 14.0 mm
For more information, see Mechanical Packaging and Orderable Information.

Functional Block Diagram

Figure 1-1 shows the CPU system and associated peripherals.

TMS320F28076 TMS320F28075 fbd_prs902.gif Figure 1-1 Functional Block Diagram