SPRS584K April 2009  – June 2016 TMS320F28030 , TMS320F28031 , TMS320F28032 , TMS320F28033 , TMS320F28034 , TMS320F28035

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
      1. 5.4.1Reducing Current Consumption
      2. 5.4.2Current Consumption Graphs (VREG Enabled)
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics
      1. 5.6.1PN Package
      2. 5.6.2PAG Package
      3. 5.6.3RSH Package
    7. 5.7 Thermal Design Considerations
    8. 5.8 Emulator Connection Without Signal Buffering for the MCU
    9. 5.9 Parameter Information
      1. 5.9.1Timing Parameter Symbology
      2. 5.9.2General Notes on Timing Parameters
    10. 5.10Test Load Circuit
    11. 5.11Power Sequencing
    12. 5.12Clock Specifications
      1. 5.12.1Device Clock Table
      2. 5.12.2Clock Requirements and Characteristics
    13. 5.13Flash Timing
  6. 6Detailed Description
    1. 6.1Overview
      1. 6.1.1  CPU
      2. 6.1.2  Control Law Accelerator (CLA)
      3. 6.1.3 Memory Bus (Harvard Bus Architecture)
      4. 6.1.4 Peripheral Bus
      5. 6.1.5 Real-Time JTAG and Analysis
      6. 6.1.6 Flash
      7. 6.1.7 M0, M1 SARAMs
      8. 6.1.8 L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 6.1.9 Boot ROM
        1. 6.1.9.1Emulation Boot
        2. 6.1.9.2GetMode
        3. 6.1.9.3Peripheral Pins Used by the Bootloader
      10. 6.1.10Security
      11. 6.1.11Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12External Interrupts (XINT1-XINT3)
      13. 6.1.13Internal Zero Pin Oscillators, Oscillator, and PLL
      14. 6.1.14Watchdog
      15. 6.1.15Peripheral Clocking
      16. 6.1.16Low-power Modes
      17. 6.1.17Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.1932-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20Control Peripherals
      21. 6.1.21Serial Port Peripherals
    2. 6.2Memory Maps
    3. 6.3Register Maps
    4. 6.4Device Emulation Registers
    5. 6.5VREG/BOR/POR
      1. 6.5.1On-chip Voltage Regulator (VREG)
        1. 6.5.1.1Using the On-chip VREG
        2. 6.5.1.2Disabling the On-chip VREG
      2. 6.5.2On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 6.6System Control
      1. 6.6.1Internal Zero Pin Oscillators
      2. 6.6.2Crystal Oscillator Option
      3. 6.6.3PLL-Based Clock Module
      4. 6.6.4Loss of Input Clock (NMI Watchdog Function)
      5. 6.6.5CPU-Watchdog Module
    7. 6.7Low-power Modes Block
    8. 6.8Interrupts
      1. 6.8.1External Interrupts
        1. 6.8.1.1External Interrupt Electrical Data/Timing
    9. 6.9Peripherals
      1. 6.9.1 Control Law Accelerator (CLA) Overview
      2. 6.9.2 Analog Block
        1. 6.9.2.1Analog-to-Digital Converter (ADC)
          1. 6.9.2.1.1Features
          2. 6.9.2.1.2ADC Start-of-Conversion Electrical Data/Timing
          3. 6.9.2.1.3On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. 6.9.2.1.3.1Internal Temperature Sensor
            2. 6.9.2.1.3.2ADC Power-Up Control Bit Timing
            3. 6.9.2.1.3.3ADC Sequential and Simultaneous Timings
        2. 6.9.2.2ADC MUX
        3. 6.9.2.3Comparator Block
          1. 6.9.2.3.1On-Chip Comparator/DAC Electrical Data/Timing
      3. 6.9.3 Detailed Descriptions
      4. 6.9.4 Serial Peripheral Interface (SPI) Module
        1. 6.9.4.1SPI Master Mode Electrical Data/Timing
        2. 6.9.4.2SPI Slave Mode Electrical Data/Timing
      5. 6.9.5 Serial Communications Interface (SCI) Module
      6. 6.9.6 Local Interconnect Network (LIN)
      7. 6.9.7 Enhanced Controller Area Network (eCAN) Module
      8. 6.9.8 Inter-Integrated Circuit (I2C)
        1. 6.9.8.1I2C Electrical Data/Timing
      9. 6.9.9 Enhanced PWM Modules (ePWM1/2/3/4/5/6/7)
        1. 6.9.9.1ePWM Electrical Data/Timing
        2. 6.9.9.2Trip-Zone Input Timing
      10. 6.9.10High-Resolution PWM (HRPWM)
        1. 6.9.10.1HRPWM Electrical Data/Timing
      11. 6.9.11Enhanced Capture Module (eCAP1)
        1. 6.9.11.1eCAP Electrical Data/Timing
      12. 6.9.12High-Resolution Capture (HRCAP) Module
        1. 6.9.12.1HRCAP Electrical Data/Timing
      13. 6.9.13Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.9.13.1eQEP Electrical Data/Timing
      14. 6.9.14JTAG Port
      15. 6.9.15General-Purpose Input/Output (GPIO) MUX
        1. 6.9.15.1GPIO Electrical Data/Timing
          1. 6.9.15.1.1 GPIO - Output Timing
          2. 6.9.15.1.2 GPIO - Input Timing
          3. 6.9.15.1.3Sampling Window Width for Input Signals
          4. 6.9.15.1.4Low-Power Mode Wakeup Timing
  7. 7Applications, Implementation, and Layout
    1. 7.1TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1Getting Started
    2. 8.2Device and Development Support Tool Nomenclature
    3. 8.3Tools and Software
    4. 8.4Documentation Support
    5. 8.5Related Links
    6. 8.6Community Resources
    7. 8.7Trademarks
    8. 8.8Electrostatic Discharge Caution
    9. 8.9Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1Packaging Information

1 Device Overview

1.1 Features

  • High-Efficiency 32-Bit CPU (TMS320C28x)
    • 60 MHz (16.67-ns Cycle Time)
    • 16 × 16 and 32 × 32 MAC Operations
    • 16 × 16 Dual MAC
    • Harvard Bus Architecture
    • Atomic Operations
    • Fast Interrupt Response and Processing
    • Unified Memory Programming Model
    • Code-Efficient (in C/C++ and Assembly)
  • Programmable Control Law Accelerator (CLA)
    • 32-Bit Floating-Point Math Accelerator
    • Executes Code Independently of the Main CPU
  • Endianness: Little Endian
  • JTAG Boundary Scan Support
    • IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
  • Low Cost for Both Device and System:
    • Single 3.3-V Supply
    • No Power Sequencing Requirement
    • Integrated Power-on Reset and Brown-out Reset
    • Low Power
    • No Analog Support Pins
  • Clocking:
    • Two Internal Zero-Pin Oscillators
    • On-Chip Crystal Oscillator and External Clock Input
    • Watchdog Timer Module
    • Missing Clock Detection Circuitry
  • Up to 45 Individually Programmable, Multiplexed GPIO Pins With Input Filtering
  • Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts
  • Three 32-Bit CPU Timers
  • Independent 16-Bit Timer in Each Enhanced Pulse Width Modulator (ePWM)
  • On-Chip Memory
    • Flash, SARAM, OTP, Boot ROM Available
  • Code-Security Module
  • 128-Bit Security Key and Lock
    • Protects Secure Memory Blocks
    • Prevents Firmware Reverse Engineering
  • Serial Port Peripherals
    • One Serial Communications Interface (SCI) Universal Asynchronous Receiver/Transmitter (UART) Module
    • Two Serial Peripheral Interface (SPI) Modules
    • One Inter-Integrated-Circuit (I2C) Module
    • One Local Interconnect Network (LIN) Module
    • One Enhanced Controller Area Network (eCAN) Module
  • Enhanced Control Peripherals
    • ePWM
    • High-Resolution PWM (HRPWM)
    • Enhanced Capture (eCAP) Module
    • High-Resolution Input Capture (HRCAP) Module
    • Enhanced Quadrature Encoder Pulse (eQEP) Module
    • Analog-to-Digital Converter (ADC)
    • On-Chip Temperature Sensor
    • Comparator
  • Advanced Emulation Features
    • Analysis and Breakpoint Functions
    • Real-Time Debug Through Hardware
  • 2803x Packages
    • 56-Pin RSH Very Thin Quad Flatpack (No Lead) (VQFN)
    • 64-Pin PAG Thin Quad Flatpack (TQFP)
    • 80-Pin PN Low-Profile Quad Flatpack (LQFP)

1.2 Applications

  • Smart Grid and Power Line Communications
  • White Goods
  • Switch Mode Power Supplies (SMPSs)
  • DC-DC Multiple-Output Power Supplies
  • Solar Micro Inverters and Converters
  • Power Factor Correction
  • Sewing and Textile Machines
  • AC-DC Inverters

1.3 Description

The F2803x Piccolo™ family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration.

An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE
TMS320F28035PNLQFP (80)12.0 mm × 12.0 mm
TMS320F28034PNLQFP (80)12.0 mm × 12.0 mm
TMS320F28033PNLQFP (80)12.0 mm × 12.0 mm
TMS320F28032PNLQFP (80)12.0 mm × 12.0 mm
TMS320F28031PNLQFP (80)12.0 mm × 12.0 mm
TMS320F28030PNLQFP (80)12.0 mm × 12.0 mm
TMS320F28035PAGTQFP (64)10.0 mm × 10.0 mm
TMS320F28034PAGTQFP (64)10.0 mm × 10.0 mm
TMS320F28033PAGTQFP (64)10.0 mm × 10.0 mm
TMS320F28032PAGTQFP (64)10.0 mm × 10.0 mm
TMS320F28031PAGTQFP (64)10.0 mm × 10.0 mm
TMS320F28030PAGTQFP (64)10.0 mm × 10.0 mm
TMS320F28035RSHVQFN (56)7.0 mm × 7.0 mm
TMS320F28034RSHVQFN (56)7.0 mm × 7.0 mm
TMS320F28033RSHVQFN (56)7.0 mm × 7.0 mm
TMS320F28032RSHVQFN (56)7.0 mm × 7.0 mm
TMS320F28031RSHVQFN (56)7.0 mm × 7.0 mm
TMS320F28030RSHVQFN (56)7.0 mm × 7.0 mm
(1) For more information on these devices, see Section 9, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram for the device.

TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 piccolo_bd_prs584.gif
A. Not all peripheral pins are available at the same time due to multiplexing.
Figure 1-1 Functional Block Diagram