SPRS523L November 2008  – December 2017 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28023 , TMS320F28026 , TMS320F28027

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings - Automotive
    3. 5.3 ESD Ratings - Commercial
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Consumption Summary
      1. 5.5.1Reducing Current Consumption
      2. 5.5.2Current Consumption Graphs (VREG Enabled)
    6. 5.6 Electrical Characteristics
    7. 5.7 Thermal Resistance Characteristics
      1. 5.7.1PT Package
      2. 5.7.2DA Package
    8. 5.8 Thermal Design Considerations
    9. 5.9 Emulator Connection Without Signal Buffering for the MCU
    10. 5.10Parameter Information
      1. 5.10.1Timing Parameter Symbology
      2. 5.10.2General Notes on Timing Parameters
    11. 5.11Test Load Circuit
    12. 5.12Power Sequencing
    13. 5.13Clock Specifications
      1. 5.13.1Device Clock Table
      2. 5.13.2Clock Requirements and Characteristics
    14. 5.14Flash Timing
  6. 6Detailed Description
    1. 6.1Overview
      1. 6.1.1  CPU
      2. 6.1.2 Memory Bus (Harvard Bus Architecture)
      3. 6.1.3 Peripheral Bus
      4. 6.1.4 Real-Time JTAG and Analysis
      5. 6.1.5 Flash
      6. 6.1.6 M0, M1 SARAMs
      7. 6.1.7 L0 SARAM
      8. 6.1.8 Boot ROM
        1. 6.1.8.1Emulation Boot
        2. 6.1.8.2GetMode
        3. 6.1.8.3Peripheral Pins Used by the Bootloader
      9. 6.1.9 Security
      10. 6.1.10Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11External Interrupts (XINT1-XINT3)
      12. 6.1.12Internal Zero Pin Oscillators, Oscillator, and PLL
      13. 6.1.13Watchdog
      14. 6.1.14Peripheral Clocking
      15. 6.1.15Low-power Modes
      16. 6.1.16Peripheral Frames 0, 1, 2 (PFn)
      17. 6.1.17General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.1832-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19Control Peripherals
      20. 6.1.20Serial Port Peripherals
    2. 6.2Memory Maps
    3. 6.3Register Maps
    4. 6.4Device Emulation Registers
    5. 6.5VREG/BOR/POR
      1. 6.5.1On-chip Voltage Regulator (VREG)
        1. 6.5.1.1Using the On-chip VREG
        2. 6.5.1.2Disabling the On-chip VREG
      2. 6.5.2On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 6.6System Control
      1. 6.6.1Internal Zero Pin Oscillators
      2. 6.6.2Crystal Oscillator Option
      3. 6.6.3PLL-Based Clock Module
      4. 6.6.4Loss of Input Clock (NMI Watchdog Function)
      5. 6.6.5CPU-Watchdog Module
    7. 6.7Low-power Modes Block
    8. 6.8Interrupts
      1. 6.8.1External Interrupts
        1. 6.8.1.1External Interrupt Electrical Data/Timing
    9. 6.9Peripherals
      1. 6.9.1 Analog Block
        1. 6.9.1.1Analog-to-Digital Converter (ADC)
          1. 6.9.1.1.1Features
          2. 6.9.1.1.2ADC Start-of-Conversion Electrical Data/Timing
          3. 6.9.1.1.3On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. 6.9.1.1.3.1Internal Temperature Sensor
            2. 6.9.1.1.3.2ADC Power-Up Control Bit Timing
            3. 6.9.1.1.3.3ADC Sequential and Simultaneous Timings
        2. 6.9.1.2ADC MUX
        3. 6.9.1.3Comparator Block
          1. 6.9.1.3.1On-Chip Comparator/DAC Electrical Data/Timing
      2. 6.9.2 Detailed Descriptions
      3. 6.9.3 Serial Peripheral Interface (SPI) Module
        1. 6.9.3.1SPI Master Mode Electrical Data/Timing
        2. 6.9.3.2SPI Slave Mode Electrical Data/Timing
      4. 6.9.4 Serial Communications Interface (SCI) Module
      5. 6.9.5 Inter-Integrated Circuit (I2C)
        1. 6.9.5.1I2C Electrical Data/Timing
      6. 6.9.6 Enhanced PWM Modules (ePWM1/2/3/4)
        1. 6.9.6.1ePWM Electrical Data/Timing
        2. 6.9.6.2Trip-Zone Input Timing
      7. 6.9.7 High-Resolution PWM (HRPWM)
        1. 6.9.7.1HRPWM Electrical Data/Timing
      8. 6.9.8 Enhanced Capture Module (eCAP1)
        1. 6.9.8.1eCAP Electrical Data/Timing
      9. 6.9.9 JTAG Port
      10. 6.9.10General-Purpose Input/Output (GPIO) MUX
        1. 6.9.10.1GPIO Electrical Data/Timing
          1. 6.9.10.1.1 GPIO - Output Timing
          2. 6.9.10.1.2 GPIO - Input Timing
          3. 6.9.10.1.3Sampling Window Width for Input Signals
          4. 6.9.10.1.4Low-Power Mode Wakeup Timing
  7. 7Applications, Implementation, and Layout
    1. 7.1TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1Getting Started
    2. 8.2Device and Development Support Tool Nomenclature
    3. 8.3Tools and Software
    4. 8.4Documentation Support
    5. 8.5Related Links
    6. 8.6Community Resources
    7. 8.7Trademarks
    8. 8.8Electrostatic Discharge Caution
    9. 8.9Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1Packaging Information

Device Overview

Features

  • High-Efficiency 32-Bit CPU (TMS320C28x)
    • 60 MHz (16.67-ns Cycle Time)
    • 50 MHz (20-ns Cycle Time)
    • 40 MHz (25-ns Cycle Time)
    • 16 × 16 and 32 × 32 MAC Operations
    • 16 × 16 Dual MAC
    • Harvard Bus Architecture
    • Atomic Operations
    • Fast Interrupt Response and Processing
    • Unified Memory Programming Model
    • Code-Efficient (in C/C++ and Assembly)
  • Endianness: Little Endian
  • Low Cost for Both Device and System:
    • Single 3.3-V Supply
    • No Power Sequencing Requirement
    • Integrated Power-on and Brown-out Resets
    • Small Packaging, as Low as 38-Pin Available
    • Low Power
    • No Analog Support Pins
  • Clocking:
    • Two Internal Zero-Pin Oscillators
    • On-Chip Crystal Oscillator and External Clock Input
    • Watchdog Timer Module
    • Missing Clock Detection Circuitry
  • Up to 22 Individually Programmable, Multiplexed GPIO Pins With Input Filtering
  • Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts
  • Three 32-Bit CPU Timers
  • Independent 16-Bit Timer in Each Enhanced Pulse Width Modulator (ePWM)
  • On-Chip Memory
    • Flash, SARAM, OTP, Boot ROM Available
  • Code-Security Module
  • 128-Bit Security Key and Lock
    • Protects Secure Memory Blocks
    • Prevents Firmware Reverse Engineering
  • Serial Port Peripherals
    • One Serial Communications Interface (SCI) Universal Asynchronous Receiver/Transmitter (UART) Module
    • One Serial Peripheral Interface (SPI) Module
    • One Inter-Integrated-Circuit (I2C) Module
  • Enhanced Control Peripherals
    • ePWM
    • High-Resolution PWM (HRPWM)
    • Enhanced Capture (eCAP) Module
    • Analog-to-Digital Converter (ADC)
    • On-Chip Temperature Sensor
    • Comparator
  • Advanced Emulation Features
    • Analysis and Breakpoint Functions
    • Real-Time Debug Through Hardware
  • Package Options
    • 38-Pin DA Thin Shrink Small-Outline Package (TSSOP)
    • 48-Pin PT Low-Profile Quad Flatpack (LQFP)
  • Temperature Options
    • T: –40°C to 105°C
    • S: –40°C to 125°C
    • Q: –40°C to 125°C
      (AEC Q100 Qualification for Automotive Applications)

Description

The F2802x Piccolo™ family of microcontrollers provides the power of the C28x core coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration.

An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE
TMS320F28027PTLQFP (48)7.0 mm × 7.0 mm
TMS320F28026PTLQFP (48)7.0 mm × 7.0 mm
TMS320F28023PTLQFP (48)7.0 mm × 7.0 mm
TMS320F28022PTLQFP (48)7.0 mm × 7.0 mm
TMS320F28021PTLQFP (48)7.0 mm × 7.0 mm
TMS320F28020PTLQFP (48)7.0 mm × 7.0 mm
TMS320F280200PTLQFP (48)7.0 mm × 7.0 mm
TMS320F28027DATSSOP (38)12.5 mm × 6.2 mm
TMS320F28026DATSSOP (38)12.5 mm × 6.2 mm
TMS320F28023DATSSOP (38)12.5 mm × 6.2 mm
TMS320F28022DATSSOP (38)12.5 mm × 6.2 mm
TMS320F28021DATSSOP (38)12.5 mm × 6.2 mm
TMS320F28020DATSSOP (38)12.5 mm × 6.2 mm
TMS320F280200DATSSOP (38)12.5 mm × 6.2 mm
For more information on these devices, see Mechanical, Packaging, and Orderable Information.

Functional Block Diagram

Figure 1-1 shows the functional block diagram for the device.

TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200 piccolo_bd_prs523.gif
Not all peripheral pins are available at the same time due to multiplexing.
Figure 1-1 Functional Block Diagram