SPRS377F September   2008  – June 2014 TMS320C6745 , TMS320C6747

PRODUCTION DATA.  

  1. 1TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. Table 3-4 C6747 Top Level Memory Map
      2. Table 3-5 C6745 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.6.4  External Memory Interface A (ASYNC, SDRAM)
      5. 3.6.5  External Memory Interface B (only SDRAM)
      6. 3.6.6  Serial Peripheral Interface Modules (SPI0, SPI1)
      7. 3.6.7  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      8. 3.6.8  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      9. 3.6.9  Enhanced Quadrature Encoder Pulse Module (eQEP)
      10. 3.6.10 Boot
      11. 3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      12. 3.6.12 Inter-Integrated Circuit Modules (I2C0, I2C1)
      13. 3.6.13 Timers
      14. 3.6.14 Universal Host-Port Interface (UHPI)
      15. 3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
      16. 3.6.16 Universal Serial Bus Modules (USB0, USB1)
      17. 3.6.17 Ethernet Media Access Controller (EMAC)
      18. 3.6.18 Multimedia Card/Secure Digital (MMC/SD)
      19. 3.6.19 Liquid Crystal Display Controller (LCD)
      20. 3.6.20 General Purpose Input Output (GPIO)
      21. 3.6.21 Reserved and No Connect
      22. 3.6.22 Supply and Ground
      23. 3.6.23 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-on Sequence
      2. 6.3.2 Power-off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 PLL Controller 0 Registers
    7. 6.7  Interrupts
      1. 6.7.1 DSP Interrupts
    8. 6.8  General-Purpose Input/Output (GPIO)
      1. 6.8.1 GPIO Register Description(s)
      2. 6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-9  Timing Requirements for GPIO Inputs (see )
        2. Table 6-10 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-11 Timing Requirements for External Interrupts (see )
    9. 6.9  EDMA
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface A (EMIFA) Registers
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-19 EMIFA SDRAM Interface Timing Requirements
        2. Table 6-20 EMIFA SDRAM Interface Switching Characteristics
        3. Table 6-21 EMIFA Asynchronous Memory Timing Requirements
        4. Table 6-22 EMIFA Asynchronous Memory Switching Characteristics
    11. 6.11 External Memory Interface B (EMIFB)
      1. 6.11.1 EMIFB SDRAM Loading Limitations
      2. 6.11.2 Interfacing to SDRAM
      3. 6.11.3 EMIFB Electrical Data/Timing
        1. Table 6-26 EMIFB SDRAM Interface Timing Requirements
        2. Table 6-27 EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature Range
        3. Table 6-28 EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive Temperature Ranges
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-32 Timing Requirements for MMC/SD Module (see and )
        2. Table 6-33 Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module (see through )
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Peripheral Register Description(s)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Registers
      2. 6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-41 Timing Requirements for MDIO Input (see and )
        2. Table 6-42 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    16. 6.16 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
      1. 6.16.1 McASP Peripheral Registers Description(s)
      2. 6.16.2 McASP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-47 McASP0 Timing Requirements
          2. Table 6-48 McASP0 Switching Characteristics
        2. 6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
          1. Table 6-49 McASP1 Timing Requirements
          2. Table 6-50 McASP1 Switching Characteristics
        3. 6.16.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
          1. Table 6-51 McASP2 Timing Requirements
          2. Table 6-52 McASP2 Switching Characteristics
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-54 General Timing Requirements for SPI0 Master Modes
          2. Table 6-55 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-56 Additional SPI0 Master Timings, 4-Pin Enable Option
          4. Table 6-57 Additional SPI0 Master Timings, 4-Pin Chip Select Option
          5. Table 6-58 Additional SPI0 Master Timings, 5-Pin Option
          6. Table 6-59 Additional SPI0 Slave Timings, 4-Pin Enable Option
          7. Table 6-60 Additional SPI0 Slave Timings, 4-Pin Chip Select Option
          8. Table 6-61 Additional SPI0 Slave Timings, 5-Pin Option
          9. Table 6-62 General Timing Requirements for SPI1 Master Modes
          10. Table 6-63 General Timing Requirements for SPI1 Slave Modes
          11. Table 6-64 Additional SPI1 Master Timings, 4-Pin Enable Option
          12. Table 6-65 Additional SPI1 Master Timings, 4-Pin Chip Select Option
          13. Table 6-66 Additional SPI1 Master Timings, 5-Pin Option
          14. Table 6-67 Additional SPI1 Slave Timings, 4-Pin Enable Option
          15. Table 6-68 Additional SPI1 Slave Timings, 4-Pin Chip Select Option
          16. Table 6-69 Additional SPI1 Slave Timings, 5-Pin Option
    18. 6.18 Enhanced Capture (eCAP) Peripheral
      1. Table 6-71 Enhanced Capture (eCAP) Timing Requirement
      2. Table 6-72 eCAP Switching Characteristics
    19. 6.19 Enhanced Quadrature Encoder (eQEP) Peripheral
      1. Table 6-74 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
      2. Table 6-75 eQEP Switching Characteristics
    20. 6.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-77 eHRPWM Timing Requirements
        2. Table 6-78 eHRPWM Switching Characteristics
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 LCD Controller
      1. 6.21.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.21.2 LCD Raster Mode
        1. Table 6-84 LCD Raster Mode Timing
    22. 6.22 Timers
      1. 6.22.1 Timer Electrical Data/Timing
        1. Table 6-86 Timing Requirements for Timer Input (see )
        2. Table 6-87 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    23. 6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 6.23.1 I2C Device-Specific Information
      2. 6.23.2 I2C Peripheral Registers Description(s)
      3. 6.23.3 I2C Electrical Data/Timing
        1. 6.23.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-89 I2C Input Timing Requirements
          2. Table 6-90 I2C Switching Characteristics
    24. 6.24 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.24.1 UART Peripheral Registers Description(s)
      2. 6.24.2 UART Electrical Data/Timing
        1. Table 6-92 Timing Requirements for UARTx Receive (see )
        2. Table 6-93 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    25. 6.25 USB1 Host Controller Registers (USB1.1 OHCI)
      1. Table 6-95 Switching Characteristics Over Recommended Operating Conditions for USB1
      2. 6.25.1     USB1 Unused Signal Configuration
    26. 6.26 USB0 OTG (USB2.0 OTG)
      1. 6.26.1 USB2.0 Electrical Data/Timing
        1. Table 6-97 Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see )
      2. 6.26.2 USB0 Unused Signal Configuration
    27. 6.27 Host-Port Interface (UHPI)
      1. 6.27.1 HPI Device-Specific Information
      2. 6.27.2 HPI Peripheral Register Description(s)
      3. 6.27.3 HPI Electrical Data/Timing
        1. Table 6-99  Timing Requirements for Host-Port Interface Cycles
        2. Table 6-100 Switching Characteristics for Host-Port Interface Cycles
    28. 6.28 Power and Sleep Controller (PSC)
      1. 6.28.1 Power Domain and Module Topology
        1. 6.28.1.1 Power Domain States
        2. 6.28.1.2 Module States
    29. 6.29 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.29.1 PRUSS Register Descriptions
    30. 6.30 Emulation Logic
      1. 6.30.1 JTAG Port Description
      2. 6.30.2 Scan Chain Configuration Parameters
      3. 6.30.3 JTAG 1149.1 Boundary Scan Considerations
    31. 6.31 IEEE 1149.1 JTAG
      1. 6.31.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
      2. 6.31.2 JTAG Test-Port Electrical Data/Timing
        1. Table 6-115 Timing Requirements for JTAG Test Port (see )
        2. Table 6-116 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
    32. 6.32 Real Time Clock (RTC)
      1. 6.32.1 Clock Source
      2. 6.32.2 Real-Time Clock Registers
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Support Resources
    4. 7.4 Related Links
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZKB
    2. 8.2 Thermal Data for PTP
    3. 8.3 Supplementary Information About the 176-pin PTP PowerPAD™ Package
      1. 8.3.1 Standoff Height
      2. 8.3.2 PowerPAD™ PCB Footprint
    4. 8.4 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZKB|256
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Mechanical Packaging and Orderable Information

This section describes the C6745/6747 orderable part numbers, packaging options, materials, thermal and mechanical parameters.

This section contains mechanical drawings for the ZKB Plastic Ball Grid Array package and the PTP PowerPAD™ plastic quad flat pack package. Additionally, for the PTP package a detailed drawing of the actual thermal pad dimensions as well as a recommended PCB footprint are provided.

7.1 Thermal Data for ZKB

The following table(s) show the thermal resistance characteristics for the PBGA–ZKB mechanical package.

Table 7-1 Thermal Resistance Characteristics (PBGA Package) [ZKB]

No. °C/W(1) °C/W(2) AIR FLOW (m/s)(3)
1 RΘJC Junction-to-case 12.8 13.5 N/A
2 RΘJB Junction-to-board 15.1 19.7 N/A
3 RΘJA Junction-to-free air 24.5 33.8 0.00
4 RΘJMA Junction-to-moving air 21.9 30 0.50
5 21.1 28.7 1.00
6 20.4 27.4 2.00
7 19.6 26 4.00
8 PsiJT Junction-to-package top 0.6 0.8 0.00
9 0.8 1 0.50
10 0.9 1.2 1.00
11 1.1 1.4 2.00
12 1.3 1.8 4.00
13 PsiJB Junction-to-board 14.9 19.1 0.00
14 14.4 18.2 0.50
15 14.4 18 1.00
16 14.3 17.7 2.00
17 14.1 17.4 4.00
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. Power dissipation of 1W and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and 1.5oz (50um) inner copper thickness
(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness. Power dissipation of 1W and ambient temp of 70C assumed.
(3) m/s = meters per second

7.2 Thermal Data for PTP

The following table(s) show the thermal resistance characteristics for the PowerPAD™ PTP mechanical package.

Table 7-2 Thermal Resistance Characteristics (PowerPAD™ Package) [PTP]"

No. °C/W(1) °C/W(2) °C/W(3) °C/W(4) AIR FLOW (m/s)(5)
1 RΘJC Junction-to-case 7.8 9.4 8.6 10.1 N/A
2 RΘJB Junction-to-board 6.2 9.9 7.1 10.6 N/A
3 RΘJA Junction-to-free air 21.3 27.9 23.2 30.6 0.00
4 RΘJMA Junction-to-moving air 14.3 20.2 22.6 0.50
5 13.1 18.6 21.0 1.00
6 12.1 17.4 19.6 2.00
7 11.2 16.2 18.2 4.00
8 PsiJT Junction-to-package top 0.5 0.7 0.8 0.00
9 0.6 0.9 1.0 0.50
10 0.7 1.0 1.1 1.00
11 0.8 1.1 1.3 2.00
12 1.0 1.3 1.5 4.00
13 PsiJB Junction-to-board 6.3 9.5 10.8 0.00
14 5.9 8.8 9.9 0.50
15 5.9 8.7 9.8 1.00
16 5.8 8.6 9.7 2.00
17 5.8 8.5 9.6 4.00
(1) Simulation data, using a model of a JEDEC defined 2S2P system with a 12mmx12mm copper pad on the top and bottom copper layers connected with an 8x8 thermal via array and soldered to the package thermal pad. Power dissipation of 1W assumed, 70C Ambient temp assumed. Signal layer copper coverage 20%, inner layer copper coverage 90%. Actual performance will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness. Power dissipation of 1W and ambient temp of 70C assumed.
(3) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper thickness 2oz (70um) top and bottom.
(4) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper thickness 1oz (35um) top and bottom.
(5) m/s = meters per second

7.3 Supplementary Information About the 176-pin PTP PowerPAD™ Package

This section highlights a few important details about the 176-pin PTP PowerPAD™ package. Texas Instruments' PowerPAD Thermally Enhanced Package Technical Brief (SLMA002) should be consulted when creating a PCB footprint for this device.

7.3.1 Standoff Height

As illustrated in Figure 7-1, the standoff height specification for this device (between 0.050 mm and 0.150 mm) is measured from the seating plane established by the three lowest package pins to the lowest point on the package body. Due to warpage, the lowest point on the package body is located in the center of the package at the exposed thermal pad.

Using this definition of standoff height provides the correct result for determining the correct solder paste thickness. According to TI's PowerPAD Thermally Enhanced Package Technical Brief (SLMA002), the recommended range of solder paste thickness for this package is between 0.152 mm and 0.178 mm.

dg_standoff_prs297.gifFigure 7-1 Standoff Height Measurement on 176-pin PTP Package

7.3.2 PowerPAD™ PCB Footprint

In general, for proper thermal performance, the thermal pad under the package body should be as large as possible. However, the soldermask opening for the PowerPAD™ should be sized to match the pad size on the 176-pin PTP package; as illustrated in Figure 7-2.

dg_solder_prs297.gifFigure 7-2 Soldermask Opening Should Match Size of DSP Thermal Pad

7.4 Packaging Information

The following packaging information and addendum reflect the most current data available for the designated device(s). This data is subject to change without notice and without revision of this document.