TMS320C6670 用于通信和电信的 4 核定点和浮点 DSP | 德州仪器 TI.com.cn

TMS320C6670
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用于通信和电信的 4 核定点和浮点 DSP

用于通信和电信的 4 核定点和浮点 DSP - TMS320C6670
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Support through a third party

This product does not have ongoing direct design support from TI. For support while working through your design, you may contact one of the following third parties: D3 Engineering, elnfochips, Ittiam Systems, Path Partner Technology, or Z3 Technologies.

描述

The TMS320C6670 Multicore Fixed and Floating Point System on Chip is a member of the C66xx SoC family based on TI's new KeyStone Multicore SoC Architecture designed specifically for high performance applications such as software defined radio, emerging broadband and other communications segments. Integrated with four C66x CorePac DSPs, each core runs at 1.0 to 1.20 GHz enabling up to 4.8 GHz. Hardware acceleration provides a highly integrated, power efficient and easy to use platform for implementing a combination of multi-band, multi-standard waveforms, including proprietary air-interfaces. The C6670 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

特性

  • Four TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.2GHz
    • 153.6 GMAC/76.8 GFLOP @ 1.2GHz
    • 32KB L1P, 32KB L1D, 1024KB L2 Per Core
    • 2MB Shared L2
  • Multicore Navigator and TeraNet Switch Fabric - 2 Tb
  • Network Coprocessors- Packet Accelerator, Security Accelerator
  • Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
  • Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
  • HyperLink - 50Gbaud Operation, Full Duplex
  • Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
  • 64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
  • Six Lane SerDes-Based Antenna Interface (AIF2) - Operating at up to 6.144 Gbps
  • Hardware Coprocessors
    • -Enhanced Coprocessor for Turbo Encoding
      -Three Enhanced Coprocessors for Turbo Decoding
      -Four Viterbi Decoders
      -Three Fast Fourier Transform Coprocessors
      -Bit Rate CoProcessor
      -Two Receiver Accelerators for WCDMA
      -Transmitt Accelerator for WCDMA
  • Four Rake Search Accelerators for Chip Rate Processing and Reed-Muller Decoding
  • I2C Interface, 16 GPIO Pins, SPI Interface
  • Eight 64-Bit Timers, Three On-Chip PLLs

参数

与其它产品相比 C6000 浮点 DSP 邮件 下载到电子表格中
Part number 立即下单 DSP On-chip L2 cache/RAM Other on-chip memory Total on-chip memory (KB) Operating systems DRAM Ethernet MAC PCI/PCIe Serial I/O I2C Approx. price (US$) SPI Operating temperature range (C) UART (SCI) Rating
TMS320C6670 立即下单 4 C66x     4096 KB     2048 KB     6528     DSP/BIOS     DDR3     10/100/1000     2 PCIe Gen2     AIF2
I2C
RapidIO
SPI
UART    
1     168.00 | 1ku     1     -40 to 100
0 to 85    
1     Catalog    
TMS320C6652 无样片 1 C66x     1024 KB     1024 KB     1088     TI-RTOS     DDR3         I2C
SPI
UART
UPP    
1     24.17 | 1ku     1     -40 to 100
0 to 85    
2     Catalog    
TMS320C6654 无样片 1 C66x     1024 KB     1024 KB     1088     DSP/BIOS     DDR3     10/100/1000     2 PCIe Gen2     I2C
SPI
UART
UPP    
1     29.73 | 1ku     1     -40 to 100
0 to 85    
2     Catalog    
TMS320C6655 无样片 1 C66x     1024 KB     1024 KB     2278     DSP/BIOS     DDR3     10/100/1000     2 PCIe Gen2     Hyperlink
I2C
RapidIO
SPI
TSIP
UART    
1     37.66 | 1ku     1     -40 to 100
0 to 85    
2     Catalog    
TMS320C6657 无样片 2 C66x     2048 KB     1024 KB     3200     DSP/BIOS     DDR3     10/100/1000     2 PCIe Gen2     Hyperlink
I2C
RapidIO
SPI
TSIP
UART    
1     37.66 | 1ku     1