产品详情

DSP type 1 C66x DSP (max) (MHz) 600 CPU 32-/64-bit Operating system TI-RTOS Ethernet MAC 10/100/1000 PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) -40 to 100
DSP type 1 C66x DSP (max) (MHz) 600 CPU 32-/64-bit Operating system TI-RTOS Ethernet MAC 10/100/1000 PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (CZH) 625 441 mm² 21 x 21
  • One TMS320C66x DSP Core Subsystem (CorePac)
    • C66x Fixed- and Floating-Point CPU Core: Up to 850 MHz for C6654 and 600 MHz for C6652
  • Multicore Shared Memory Controller (MSMC)
    • Memory Protection Unit for DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Peripherals
    • PCIe Gen2 (C6654 Only)
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • Gigabit Ethernet (GbE) Subsystem (C6654 Only)
      • One SGMII Port (C6654 Only)
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1066
      • 4GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C
  • One TMS320C66x DSP Core Subsystem (CorePac)
    • C66x Fixed- and Floating-Point CPU Core: Up to 850 MHz for C6654 and 600 MHz for C6652
  • Multicore Shared Memory Controller (MSMC)
    • Memory Protection Unit for DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Peripherals
    • PCIe Gen2 (C6654 Only)
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • Gigabit Ethernet (GbE) Subsystem (C6654 Only)
      • One SGMII Port (C6654 Only)
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1066
      • 4GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C

The C6654 and C6652 are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 850 MHz for C6654 and 600 MHz for C6652. For developers of a broad range of applications, both C6654 and C6652 DSPs enable a platform that is power-efficient and easy to use. In addition, the C6654 and C6652 DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 27.2 GMACS per core and 13.6 GFLOPS per core (@850 MHz frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI’s previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C6654 and C6652 DSPs integrate a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1066 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including PCI Express Gen2 and Gigabit Ethernet (PCIe and Gigabit Ethernet are not supported on the C6652). This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO.

The C6654 and C6652 devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, and Multicore Shared Memory Controller.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

The C6654 and C6652 are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 850 MHz for C6654 and 600 MHz for C6652. For developers of a broad range of applications, both C6654 and C6652 DSPs enable a platform that is power-efficient and easy to use. In addition, the C6654 and C6652 DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 27.2 GMACS per core and 13.6 GFLOPS per core (@850 MHz frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI’s previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C6654 and C6652 DSPs integrate a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1066 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including PCI Express Gen2 and Gigabit Ethernet (PCIe and Gigabit Ethernet are not supported on the C6652). This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO.

The C6654 and C6652 devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, and Multicore Shared Memory Controller.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

下载 观看带字幕的视频 视频

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 53
类型 标题 下载最新的英语版本 日期
* 数据表 TMS320C6652 and TMS320C6654 Fixed and Floating-Point Digital Signal Processor 数据表 (Rev. E) PDF | HTML 2019年 9月 4日
* 勘误表 TMS320C6652/54/55/57 Multicore Fixed and Floating-Point DSP SR1.0 (Rev. C) 2016年 5月 19日
应用手册 DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022年 7月 7日
应用手册 KeyStone 错误检测和校正 (Rev. A) PDF | HTML 英语版 (Rev.A) 2021年 8月 4日
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 英语版 (Rev.A) PDF | HTML 2021年 5月 19日
用户指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020年 6月 1日
应用手册 Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 2019年 6月 11日
应用手册 Keystone Bootloader Resources and FAQ 2019年 5月 29日
应用手册 Keystone Multicore Device Family Schematic Checklist PDF | HTML 2019年 5月 17日
应用手册 Hardware Design Guide for KeyStone Devices (Rev. D) 2019年 3月 21日
应用手册 KeyStone I DDR3 interface bring-up 2019年 3月 6日
应用手册 Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017年 8月 14日
用户指南 Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017年 7月 26日
应用手册 KeyStone I DDR3 Initialization (Rev. E) 2016年 10月 28日
产品概述 TMS320C6657/55/54 Power efficient high performance for process-intensive apps (Rev. A) 2016年 5月 23日
应用手册 TI DSP Benchmarking 2016年 1月 13日
应用手册 Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015年 8月 13日
用户指南 Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 2015年 5月 6日
用户指南 Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015年 4月 9日
用户指南 DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E) 2015年 1月 20日
用户指南 Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014年 9月 4日
更多文献资料 KeyStone Lab Manual - Training 2014年 6月 5日
用户指南 System Analyzer User's Guide (Rev. F) 2013年 11月 18日
用户指南 DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 2013年 7月 15日
白皮书 Accelerating high-performance computing development with Desktop Linux SDK 2013年 7月 8日
用户指南 C66x CorePac User's Guide (Rev. C) 2013年 6月 28日
用户指南 Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013年 6月 28日
产品概述 OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) 2012年 11月 5日
产品概述 TMS320C66x high-performance multicore DSPs for video surveillance 2012年 9月 6日
用户指南 Universal Parallel Port (uPP) for KeyStone Architecture User's Guide 2012年 6月 11日
用户指南 Multichannel Buffered Serial Port (MCBSP) User's Guide for KeyStone Devices 2012年 5月 25日
白皮书 Leveraging multicore processors for machine vision applications 2012年 5月 9日
用户指南 Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012年 3月 30日
用户指南 Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012年 3月 27日
白皮书 Superior performance at breakthrough size, weight & power 2012年 3月 26日
用户指南 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012年 3月 22日
用户指南 Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A) 2011年 10月 15日
应用手册 Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
用户指南 Debug and Trace for KeyStone I Devices User's Guide (Rev. A) 2011年 9月 22日
用户指南 Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011年 9月 2日
白皮书 KeyStone Multicore SoC Tool Suite: one platform for all needs 2011年 6月 17日
用户指南 External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011年 5月 24日
白皮书 Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011年 5月 19日
应用手册 TMS320C66x DSP Generation of Devices (Rev. A) 2011年 4月 25日
白皮书 “KeyStone Memory Architecture”(梯形存储器架构)白皮书 (Rev. A) 2010年 12月 21日
用户指南 C66x CPU and Instruction Set Reference Guide 2010年 11月 9日
用户指南 C66x DSP Cache User's Guide 2010年 11月 9日
应用手册 Clocking Design Guide for KeyStone Devices 2010年 11月 9日
用户指南 General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010年 11月 9日
应用手册 Optimizing Loops on the C66x DSP 2010年 11月 9日
用户指南 Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 2010年 11月 9日
用户指南 Flip Chip Ball Grid Array Package Reference Guide (Rev. A) 2005年 5月 23日
应用手册 AN-1281 Bumped Die (Flip Chip) Packages (Rev. A) 2004年 5月 1日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

评估板

TMDSEVM6657 — TMS320C6657 Lite 评估模块

TMS320C6657LS Lite 评估模块 (EVM) 是易于使用且符合成本效益的开发工具,可帮助开发人员使用 C6657、C6655 或 C6654 系列 DSP 快速着手进行设计。EVM 包括具有强大连接选项的单个板载 C6657 处理器,使客户可以在各种系统中使用此 AMC 封装卡。它还可用作独立电路板。随附 6657LS EVM 的软件包括 Code Composer Studio™ 集成开发环境版本 5 (CCS v5)、包含板级支持包 (BSP) 的 TI 多核软件开发套件 (MCSDK)、芯片支持库 (CSL)、加电自检测 (POST)、网络开发套件 (...)

TI.com 上无现货
子卡

SHELD-3P-DSP-SOMS — Sheldon DSP-FPGA 电路板

Sheldon Instruments 为 PCIe/PCI、PCI104e/PCI104、XMC/PMC 和 CompactPCI 系统设计和制造基于 DSP 的 COTS 数据采集和控制硬件,以及适用于各种应用和市场的驱动程序和实时开发软件。

如需了解有关 Sheldon 仪器的更多信息,请访问 https://sheldoninstruments.com




软件开发套件 (SDK)

PROCESSOR-SDK-RTOS-C665X 适用于 C665X 的 RTOS 处理器 SDK

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
TMS320C6652 高性能、成本优化的单核 C66x 定点和浮点 DSP - 600MHz
下载选项
IDE、配置、编译器或调试器

CCSTUDIO Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

支持的产品和硬件

支持的产品和硬件

此设计资源支持这些类别中的大部分产品。

查看产品详情页,验证是否能提供支持。

启动 下载选项
软件编解码器

VOCAL-3P-DSPVOIPCODECS — Vocal Technologies DSP VoIP 编解码器

经过 25 年以上的组装和 C 代码开发,VOCAL 的模块化软件套件可用于各种各样的 TI DSP 产品。产品具体包括 ATA、VoIP 服务器和网关、基于 HPNA 的 IPBX、视频监控、语音和视频会议、语音和数据射频器件、RoIP 网关、政务安全器件、合法拦截软件、医疗设备、嵌入式调制解调器、T.38 传真和 FoIP。

如需了解有关 Vocal Technologies 的更多信息,请访问 https://www.vocal.com
仿真模型

C6652 Power Consumption Model

SPRM676.ZIP (176 KB) - Power Model
设计工具

PROCESSORS-3P-SEARCH — 基于 Arm® 的 MPU、基于 Arm 的 MCU 和 DSP 第三方搜索工具

TI 已与多家公司合作,提供各种使用 TI 处理器的软件、工具和 SOM,从而加快您的量产速度。下载此搜索工具,快速浏览我们的第三方解决方案,并寻找合适的第三方来满足您的需求。此处所列的软件、工具和模块由独立的第三方生产和管理,而非德州仪器 (TI)。

搜索工具按产品类型划分为以下类别:

  • 工具包括 IDE/编译器、调试和跟踪、仿真和建模软件以及闪存编程器。
  • 操作系统包括 TI 处理器支持的操作系统。
  • 应用软件是指应用特定的软件,包括在 TI 处理器上运行的中间件和库。
  • SoM 是模块上系统解决方案
封装 引脚 下载
FCBGA (CZH) 625 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持和培训

视频