TMDS461

The TMDS461 is a 4-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to four DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth.

The TMDS461 provides an analog adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps (see Figure 19).

When any input port is selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.

The TMDS461 is designed to be controlled via a local I²C interface or GPIO interface based on the status of the I2C_SEL pin. The local I²C interface in TMDS461 is a slave-only I²C interface. (See the I2C INTERFACE NOTES section.)

I²C Mode: When the I2C_SEL pin is set high, the device is in I²C mode. Refer to Table 7 to Table 13 for I²C register description. With local I²C, the interface port status can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I²C buffer output-voltage-select (OVS) settings (See the DDC 12C FUNCTION DESCRIPTION for detailed description on DDC I²C buffer description and OVS description), device power management, TMDS clock-detect feature, Automatic Port Selection and TMDS input-port selection can be set. In I²C mode when any system level change such as change in 5V_PWR on the source side, a change in the selected port, or a change in the selected port's valid clock detect is detected, TMDS461 can issue an Interrupt Request via IRQ pin (refer IRQ SECTION). A micro-controller connected to TMDS461 can read I²C register address 0X01, (See Table 7) to obtain the current status of 5V_PWR, the selected port, and clock-detect status. Once the micro-controller has read I²C register 0x01, the IRQ pin returns to low.

GPIO mode: When the I2C_SEL pin is set low, the device is in GPIO control mode. The port selection is controlled with source selectors, S1 and S2. The power-saving mode is controlled through the LP pin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set. The DDC I²C buffer OVS setting can be changed through OVS GPIO pin, see Table 2. In GPIO mode, IRQ pin reflects the status of the selected port's clock detect. If a valid clock is detected by the clock detect circuit, IRQ goes high. If no valid clock is detected, IRQ is driven low.

Following are some of the key features (advantages) that TMDS461 provides to the overall sink-side system (HDTV).

• 4:1 switch that supports TMDS data rates up to 3 Gbps on all four input ports.
• ESD: Built-in support for high ESD protection (up to 10 kV on the TMDS and DDC I²C pins ). The HDMI source-side pins on the TMDS461 are connected via the HDMI/DVI exterior connectors and cable to the HDMI/DVI sources (e.g., DVD player). In TV applications, it can be expected that the source side may be subjected to higher ESD stresses compared to the sink side that is connected internally to the HDMI receiver.
• Adaptive equalization: The built-in analog adaptive equalization support compensates for intersymbol interference [ISI] loss of up to 20 dB, which represents a typical 20-m HDMI/DVI cable at 3 Gbps. Analog Adaptive equalization adjusts the equalization gain automatically, based on the cable length and the incoming TMDS data rate.
• TMDS clock-detect circuitry: This feature provides an automatic power-management feature and also ensures that the TMDS output port is turned on only if there is a valid TMDS input signal. TMDS clock-detect feature can be by-passed in I²C Mode, (See Table 9). It is recommended to enable TMDS clock-detect circuitry during normal operation. However, for HDMI compliance testing (TMDS Termination Voltage Test), the clock detect feature should be disabled by using the I²C mode control. To comply with the TMDS Termination Voltage Test in the GPIO mode (default TMDS clock-detect circuitry enabled), a valid TMDS clock will need to be provided. With the clock present, the internal terminations are present providing the correct termination voltage.
• DDC I²C buffer: This feature provides isolation on the source side and sink side DDC I²C capacitance, thus helping the sink system to pass system-level compliance.
• Robust TMDS receive stage: This feature ensures that the TMDS461 can work with TMDS input signals which have common-mode voltage levels that can be either compliant or non-compliant with HDMI/DVI specifications
• VSadj: This feature adjusts the TMDS output swing and can help the sink system to tune the output TMDS swing of the TMDS461 (if needed) based on the system requirements.
• GPIO or local I²C interface to control the device features
• TMDS output edge-rate control: This feature adjusts the TMDS461 TMDS output rise and fall times. There are four settings that can be chosen. The default setting is the fastest rise and fall time; the other three settings are slower. Slower edge transitions can potentially help the sink system (HDTV) in passing regulatory EMI compliance.
• Automatic Port Select Feature available in I²C mode
• 5V_PWR detect for each port connected, Hot Plug Detect (HPD) of non selected port follows 5V_PWR, whereas HPD of selected port follows HPD_SINK.