ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock. Figure 14 shows a timing diagram of this operation.