ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
IOVDD = 1.1 V | IOVDD = 3.3 V | UNIT | ||||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
I2S, LEFT-JUSTIFIED AND RIGHT-JUSTIFIED TIMING IN MASTER MODE (See Figure 1) | ||||||
td(WS) | ADWS, WCLK delay time | 50 | 15 | ns | ||
td(DO-WS) | ADWS, WCLK to DOUT delay time | 50 | 20 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay time | 50 | 15 | ns | ||
ts(DI) | DIN setup time | 10 | 6 | ns | ||
th(DI) | DIN hold time | 10 | 6 | ns | ||
tr | Rise time | 30 | 10 | ns | ||
tf | Fall time | 30 | 10 | ns | ||
DSP TIMING IN MASTER MODE (See Figure 2) | ||||||
td(WS) | ADWS, WCLK delay time | 50 | 15 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay time | 50 | 15 | ns | ||
ts(DI) | DIN setup time | 10 | 6 | ns | ||
th(DI) | DIN hold time | 10 | 6 | ns | ||
tr | Rise time | 30 | 10 | ns | ||
tf | Fall time | 30 | 10 | ns | ||
I2S, LEFT-JUSTIFIED AND RIGHT-JUSTIFIED TIMING IN SLAVE MODE (See Figure 3) | ||||||
tH(BCLK) | BCLK high period | 70 | 35 | ns | ||
tL(BCLK) | BCLK low period | 70 | 35 | ns | ||
ts(WS) | ADWS, WCLK setup time | 10 | 6 | ns | ||
th(WS) | ADWS, WCLK hold time | 10 | 6 | ns | ||
td(DO-WS) | ADWS, WCLK to DOUT delay time (for left-justified mode only) | 50 | 35 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay time | 50 | 20 | ns | ||
ts(DI) | DIN setup time | 10 | 6 | ns | ||
th(DI) | DIN hold time | 10 | 6 | ns | ||
tr | Rise time | 8 | 4 | ns | ||
tf | Fall time | 8 | 4 | ns | ||
DSP TIMING IN SLAVE MODE (See Figure 4) | ||||||
tH(BCLK) | BCLK high period | 70 | 35 | ns | ||
tL(BCLK) | BCLK low period | 70 | 35 | ns | ||
ts(WS) | ADWS, WCLK setup time | 10 | 8 | ns | ||
th(WS) | ADWS, WCLK hold time | 10 | 8 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay time | 50 | 20 | ns | ||
ts(DI) | DIN setup time | 10 | 6 | ns | ||
th(DI) | DIN hold time | 10 | 6 | ns | ||
tr | Rise time | 8 | 4 | ns | ||
tf | Fall time | 8 | 4 | ns |