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TLC6C598-Q1

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汽车类电源逻辑 8 位移位寄存器 LED 驱动器

产品详情

Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 3 Vin (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 40 Iout (max) (A) 0.4 Features Thermal shutdown
Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 3 Vin (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 40 Iout (max) (A) 0.4 Features Thermal shutdown
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C3B
  • Wide Vcc From 3 V to 5.5 V
  • Output Maximum Rating of.40 V
  • Eight Power DMOS Transistor Outputs of 50-mA Continuous Current With VCC = 5 V
  • Thermal Shutdown Protection
  • Enhanced Cascading for Multiple Stages
  • All Registers Cleared With Single Input
  • Low Power Consumption
  • Slow Switching Time (tr and tf), Which Helps Significantly With Reducing EMI
  • 16-Pin TSSOP-PW Package
  • 16-Pin SOIC-D Package
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C3B
  • Wide Vcc From 3 V to 5.5 V
  • Output Maximum Rating of.40 V
  • Eight Power DMOS Transistor Outputs of 50-mA Continuous Current With VCC = 5 V
  • Thermal Shutdown Protection
  • Enhanced Cascading for Multiple Stages
  • All Registers Cleared With Single Input
  • Low Power Consumption
  • Slow Switching Time (tr and tf), Which Helps Significantly With Reducing EMI
  • 16-Pin TSSOP-PW Package
  • 16-Pin SOIC-D Package

The TLC6C598-Q1 is a monolithic, medium-voltage, low-current power 8-bit shift register designed for use in systems that require relatively moderate load power, such as LEDs.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (CLR) is high. A low on CLR clears all registers in the device. Holding the output enable (G) high, holds all data in the output buffers low, and all drain outputs are off. Holding G low makes data from the storage register transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The serial output (SER OUT) clocks out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This provides improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. The device contains built-in thermal shutdown protection.

Outputs are low-side, open-drain DMOS transistors with output ratings of 40 V and 50 mA continuous sink-current capabilities when Vcc = 5 V. The current limit decreases as the junction temperature increases for additional device protection. The device also provides up to 2000 V of ESD protection when tested using the human-body model and 200 V when using the machine model.

The TLC6C598-Q1 characterization is for for operation over the operating ambient temperature range of −40°C to 125°C.

The TLC6C598-Q1 is a monolithic, medium-voltage, low-current power 8-bit shift register designed for use in systems that require relatively moderate load power, such as LEDs.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (CLR) is high. A low on CLR clears all registers in the device. Holding the output enable (G) high, holds all data in the output buffers low, and all drain outputs are off. Holding G low makes data from the storage register transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The serial output (SER OUT) clocks out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This provides improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. The device contains built-in thermal shutdown protection.

Outputs are low-side, open-drain DMOS transistors with output ratings of 40 V and 50 mA continuous sink-current capabilities when Vcc = 5 V. The current limit decreases as the junction temperature increases for additional device protection. The device also provides up to 2000 V of ESD protection when tested using the human-body model and 200 V when using the machine model.

The TLC6C598-Q1 characterization is for for operation over the operating ambient temperature range of −40°C to 125°C.

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技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 TLC6C598-Q1 Power Logic 8-Bit Shift Register LED Driver 数据表 (Rev. D) PDF | HTML 2016年 9月 13日
应用手册 TLC6C598-Q1, TLC6C5912-Q1 Shift Register LED Driver Application 2015年 6月 4日
用户指南 TLC6C598-Q1 and TLC6C5912-Q1 Reference Design 2012年 11月 29日

设计和开发

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仿真模型

TLC6C598 IBIS Model

SLIM316.ZIP (46 KB) - IBIS Model
仿真模型

TLC6C598 Unencrypted PSpice Transient Model Package (Rev. B)

SLIM311B.ZIP (29 KB) - PSpice Model
模拟工具

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参考设计

TIDA-010076 — 通过单对以太网 (T1) 实现菊花链式电源和数据传输的参考设计

TIDA-010076 展示了如何通过 SPE 传输 220W 的电力和 100Mbit/s 的数据。与星型拓扑中的常规系统相比,菊花链拓扑中的通信系统需要的硬件和布线明显更少。与单对以太网(SPE,100BASE-T1)及数据线供电结合使用时,该设计可以减少接线,实现简化。电力和数据仅通过两条导线从一个节点输送到另一个节点。
设计指南: PDF
原理图: PDF
封装 引脚 下载
SOIC (D) 16 查看选项
TSSOP (PW) 16 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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