ZHCSCU5A May   2014  – September 2014 TLC5958

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 典型应用电路（多个菊花链 TLC5958）
  5. 5 修订历史记录
  6. 6 说明（继续）
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Pin Equivalent Input and Output Schematic Diagrams
      1. 9.1.1 Test Circuits
    2. 9.2 Timing Diagrams
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Device Functional Modes
      1. 10.3.1  Brightness Control (BC) Function
      2. 10.3.2  Color Brightness Control (CC) Function
      3. 10.3.3  Select RIREF For a Given BC
      4. 10.3.4  Choosing BC/CC For a Different Application
        1. 10.3.4.1 Example 1: Red LED Current is 20mA, Green LED Needs 12mA, Blue LED needs 8mA
        2. 10.3.4.2 Example 2: Red LED Current is 5mA, Green LED Needs 2mA, Blue LED Needs 1mA.
      5. 10.3.5  LED Open Detection (LOD)
      6. 10.3.6  Power Save Mode (PSM)
      7. 10.3.7  Internal Pre-Charge FET
      8. 10.3.8  Thermal Shutdown (TSD)
      9. 10.3.9  IREF Resistor Short Protection (ISP)
      10. 10.3.10 Noise Reduction
  11. 11Application and Implementation
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14器件和文档支持
    1. 14.1 商标
    2. 14.2 静电放电警告
    3. 14.3 术语表
  15. 15机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Parameter Measurement Information

9.1 Pin Equivalent Input and Output Schematic Diagrams

sch_SIN_SCLK_slvsce7.gifFigure 11. SIN, SCLK
sch_GCLK_slvsce7.gifFigure 13. GCLK
sch_OUTR0_OUTR15_slvsce7.gif
(1) X=R or G or B, n=0~15
Figure 15. OUTR0/G0/B0 Through OUTR15/G15/B15
sch_LAT_slvsce7.gifFigure 12. LAT
sch_SOUT_slvsce7.gifFigure 14. SOUT

9.1.1 Test Circuits

sch_RT_FT_TC_OUTXn_slvsce7.gif
(1) CL includes measurement probe and jig capacitance.
(2) X=R or G or B, n=0~15
Figure 16. Rise Time and Fall Time Test Circuit for OUTXn
sch_Cc_TC_OUTXn_slvsce7.gif
(1) X=R or G or B, n=0~15
Figure 18. Constant Current Test Circuit for OUTXn
sch_RT_FT_TC_SOUT_slvsce7.gif
(1) CL includes measurement probe and jig capacitance.
Figure 17. Rise Time and Fall Time Test Circuit for SOUT

9.2 Timing Diagrams

td_input_timing_slvsce7.gif
(1) Input pulse rise and fall time is 1~3ns
(2) 8 + 8 mode (SEL_PWM=0)
Figure 19. Timing Diagrams