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TLC320AD50

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具有主从功能（3 个从器件）和 89dB SNR 的单通道编解码器

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TLC320AD50

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产品详情

Number of ADC channels 1 Number of DAC channels 1 Analog inputs 2 Analog outputs 2 Sampling rate (max) (kHz) 22.05 Rating Military ADC SNR (typ) (dB) 0 DAC SNR (typ) (dB) 0 Operating temperature range (°C) -40 to 85
Number of ADC channels 1 Number of DAC channels 1 Analog inputs 2 Analog outputs 2 Sampling rate (max) (kHz) 22.05 Rating Military ADC SNR (typ) (dB) 0 DAC SNR (typ) (dB) 0 Operating temperature range (°C) -40 to 85
SOIC (DW) 28 184.37 mm² 17.9 x 10.3
  • General-purpose analog interface circuit for V.34+ modem and business audio applications
  • 16-bit oversampling sigma-delta ADC and DAC
  • Serial port interface
  • Typical 89-dB SNR (signal-to-noise ratio) for ADC and DAC
  • Typical 90-dB THD (signal to total harmonic distortion) for ADC and DAC
  • Typical 88-dB dynamic range
  • Test mode that includes a digital loopback test and analog loopback test
  • Programmable A/D and D/A conversion rate
  • Programmable input and output gain control
  • Maximum conversion rate: 22.05 kHz
  • Single 5-V power supply voltage or 5-V analog and 3-V digital power supply voltage
  • Power dissipation (PD) of 120 mW rms typical in the operating mode
  • Hardware power-down mode to 7.5 mW
  • Internal reference voltage (Vref)
  • Differential architecture throughout device
  • TLC320AD50C/I can support up to three slave devices; TLC320AD52C can support one slave
  • 2s complement data format
  • ALTDATA terminal provides data monitoring
  • Monitor amplifier to monitor input signals
  • On-chip phase locked loop (PLL)
  • General-purpose analog interface circuit for V.34+ modem and business audio applications
  • 16-bit oversampling sigma-delta ADC and DAC
  • Serial port interface
  • Typical 89-dB SNR (signal-to-noise ratio) for ADC and DAC
  • Typical 90-dB THD (signal to total harmonic distortion) for ADC and DAC
  • Typical 88-dB dynamic range
  • Test mode that includes a digital loopback test and analog loopback test
  • Programmable A/D and D/A conversion rate
  • Programmable input and output gain control
  • Maximum conversion rate: 22.05 kHz
  • Single 5-V power supply voltage or 5-V analog and 3-V digital power supply voltage
  • Power dissipation (PD) of 120 mW rms typical in the operating mode
  • Hardware power-down mode to 7.5 mW
  • Internal reference voltage (Vref)
  • Differential architecture throughout device
  • TLC320AD50C/I can support up to three slave devices; TLC320AD52C can support one slave
  • 2s complement data format
  • ALTDATA terminal provides data monitoring
  • Monitor amplifier to monitor input signals
  • On-chip phase locked loop (PLL)

The TLC320AD50C, TLC320AD50I, and TLC320AD52C provide high-resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology. This device consists of a pair of 16-bit synchronous serial conversion paths (one for each direction) and includes an interpolation filter before the DAC and a decimation filter after the ADC. Other overhead functions on the chip include timing (sample rate, FSD delay) and control (programmable gain amplifier, PLL, communication protocol, etc.). The sigma-delta architecture produces high resolution A/D and D/A conversion at a low system cost.

Programmable functions of this device can be selected through the serial interface. Options include reset, power down, communications protocol, signal sampling rate, gain control, and system test modes (see section 6). The TLC320AD50C and TLC320AD52C are characterized for operation from 0°C to 70°C, and the TLC320AD50I is characterized for operation from \x9640°C to 85°C.

The TLC320AD50C, TLC320AD50I, and TLC320AD52C provide high-resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology. This device consists of a pair of 16-bit synchronous serial conversion paths (one for each direction) and includes an interpolation filter before the DAC and a decimation filter after the ADC. Other overhead functions on the chip include timing (sample rate, FSD delay) and control (programmable gain amplifier, PLL, communication protocol, etc.). The sigma-delta architecture produces high resolution A/D and D/A conversion at a low system cost.

Programmable functions of this device can be selected through the serial interface. Options include reset, power down, communications protocol, signal sampling rate, gain control, and system test modes (see section 6). The TLC320AD50C and TLC320AD52C are characterized for operation from 0°C to 70°C, and the TLC320AD50I is characterized for operation from \x9640°C to 85°C.
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类型 标题 下载最新的英语版本 日期
* 数据表 Sigma-Delta Analog Interface Circuits With Master-Slave Function 数据表 (Rev. E) 2000年 10月 13日
应用手册 Out-of-Band Noise Measurement Issues for Audio Devices (Rev. A) 2019年 12月 31日
应用手册 Audio Serial Interface Configurations for Audio Codecs (Rev. A) 2019年 6月 27日
应用手册 Using the MSP430 Launchpad as a Standalone I2C Host for Audio Products (Rev. A) 2013年 10月 28日
应用手册 Audio Serial Interface Configurations for Audio Codecs 2010年 9月 22日
应用手册 Solving Enumeration Errors in USB Audio DAC and CODEC Designs 2009年 10月 30日
应用手册 Configuring I2S to Generate BCLK from Codec Devices & WCLK from McBSP Port 2009年 7月 8日
EVM 用户指南 Evaluation Board for the TLC320AD50C DSP Analog Interface Circuit 2000年 2月 9日
应用手册 Comparison of TI Voiceband Codecs for Telephony Applications 1999年 12月 8日
应用手册 Design Guidelines for the TLC320AD50 1999年 12月 2日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 封装厂地点

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