ZHCSFY2A August 2015  – November 2016 TAS2555

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 SPI Timing Requirements
    8. 7.8 I2S/LJF/RJF Timing in Master Mode
    9. 7.9 I2S/LJF/RJF Timing in Slave Mode
    10. 7.10DSP Timing in Master Mode
    11. 7.11DSP Timing in Slave Mode
    12. 7.12Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1 General I2C Operation
      2. 9.3.2 Single-Byte and Multiple-Byte Transfers
      3. 9.3.3 Single-Byte Write
      4. 9.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.3.5 Single-Byte Read
      6. 9.3.6 Multiple-Byte Read
      7. 9.3.7 General SPI Operation
      8. 9.3.8 Class-D Edge Rate Control
      9. 9.3.9 Battery Tracking AGC
      10. 9.3.10Configurable Boost Current Limit (ILIM)
        1. 9.3.10.1Fault Protection
          1. 9.3.10.1.1OverCurrent
          2. 9.3.10.1.2Analog Undervoltage
          3. 9.3.10.1.3Overtemperature
          4. 9.3.10.1.4Clocking Faults
        2. 9.3.10.2Brownout
        3. 9.3.10.3Spread Spectrum vs Synchronized
        4. 9.3.10.4IRQs and Flags
        5. 9.3.10.5Software Reset
        6. 9.3.10.6PurePath Console 3 Software TAS2555 Application
    4. 9.4Device Functional Modes
      1. 9.4.1Audio Digital I/O Interface
        1. 9.4.1.1Right-Justified Mode (RJF)
        2. 9.4.1.2Left-Justified Mode (LJF)
        3. 9.4.1.3I2S Mode
        4. 9.4.1.4DSP Mode
      2. 9.4.2TDM Mode
      3. 9.4.3Device Digital Processing Modes
        1. 9.4.3.1ROM Mode 1
        2. 9.4.3.2ROM Mode 2
        3. 9.4.3.3SmartAmp Mode
      4. 9.4.4Low Power Sleep Mode
    5. 9.5Programming
      1. 9.5.1Code Loading and CRC check
      2. 9.5.2Device Power Up, Power Down, Mute and Un-mute Sequence
  10. 10Applications and Implementation
    1. 10.1Application Information
    2. 10.2Typical Applications
      1. 10.2.1Design Requirements
        1. 10.2.1.1Detailed Design Procedure
          1. 10.2.1.1.1Mono/Stereo Configuration
          2. 10.2.1.1.2Boost Converter Passive Devices
          3. 10.2.1.1.3EMI Passive Devices
          4. 10.2.1.1.4Miscellaneous Passive Devices
      2. 10.2.2Application Performance Plots
    3. 10.3Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1Power Supplies
    2. 11.2Power Supply Sequencing
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Register Map
    1. 13.1Register Map Summary
    2. 13.2 Book 0 Page 0
      1. 13.2.1 Book 0 / Page 0 / Register 0: Page Select Register - 0x00 / 0x00 / 0x00 (B0_P0_R0)
      2. 13.2.2 Book 0 / Page 0 / Register 1: Software Reset Register - 0x00 / 0x00 / 0x01 (B0_P0_R1)
      3. 13.2.3 Book 0 / Page 0 / Register 2-3: Reserved Registers - 0x00 / 0x00 / 0x02-0x03 (B0_P0_R2-3)
      4. 13.2.4 Book 0 / Page 0 / Register 4: Power Control Register - 0x00 / 0x00 / 0x04 (B0_P0_R4)
      5. 13.2.5 Book 0 / Page 0 / Register 5: Power Control Register 2 - 0x00 / 0x00 / 0x05 (B0_P0_R5)
      6. 13.2.6 Book 0 / Page 0 / Register 6: Speaker Control Register - 0x00 / 0x00 / 0x06 (B0_P0_R6)
      7. 13.2.7 Book 0 / Page 0 / Register 7: Mute Register - 0x00 / 0x00 / 0x07 (B0_P0_R7)
      8. 13.2.8 Book 0 / Page 0 / Register 8: Channel Control Register - 0x00 / 0x00 / 0x08 (B0_P0_R8)
      9. 13.2.9 Book 0 / Page 0 / Register 9-31: Reserved Registers - 0x00 / 0x00 / 0x09-0x1F (B0_P0_R9-31)
      10. 13.2.10Book 0 / Page 0 / Register 32: CRC Checksum Register - 0x00 / 0x00 / 0x20 (B0_P0_R32)
      11. 13.2.11Book 0 / Page 0 / Register 33: Checksum Reset Register - 0x00 / 0x00 / 0x21 (B0_P0_R33)
      12. 13.2.12Book 0 / Page 0 / Register 34: Device DSP Mode Register - 0x00 / 0x00 / 0x22 (B0_P0_R34)
      13. 13.2.13Book 0 / Page 0 / Register 35-39: Reserved Registers - 0x00 / 0x00 / 0x23-0x27 (B0_P0_R35-R39)
      14. 13.2.14Book 0 / Page 0 / Register 40: Class-D SSM Mode Register - 0x00 / 0x00 / 0x28 (B0_P0_R40)
      15. 13.2.15Book 0 / Page 0 / Register 41: Reserved Registers - 0x00 / 0x00 / 0x29 (B0_P0_R41)
      16. 13.2.16Book 0 / Page 0 / Register 42: Digital Playback Control Register - 0x00 / 0x00 / 0x2A (B0_P0_R42)
      17. 13.2.17Book 0 / Page 0 / Register 43: Current Limit Register - 0x00 / 0x00 / 0x2B (B0_P0_R43)
      18. 13.2.18Book 0 / Page 0 / Register 44: Clock Error Control 1 Register - 0x00 / 0x00 / 0x2C (B0_P0_R44)
      19. 13.2.19Book 0 / Page 0 / Register 45: Clock Error Control 2 Register - 0x00 / 0x00 / 0x2D (B0_P0_R45)
      20. 13.2.20Book 0 / Page 0 / Register 46: Clock Error Control 3 Register - 0x00 / 0x00 / 0x2E (B0_P0_R46)
      21. 13.2.21Book 0 / Page 0 / Register 47-99: Reserved Registers - 0x00 / 0x00 / 0x2F-0x63 (B0_P0_R47-R99)
      22. 13.2.22Book 0 / Page 0 / Register 100: Power Up Flag Register - 0x00 / 0x00 / 0x64 (B0_P0_R100)
      23. 13.2.23Book 0 / Page 0 / Register 101-103: Reserved Registers - 0x00 / 0x00 / 0x65-0x67 (B0_P0_R101-R103)
      24. 13.2.24Book 0 / Page 0 / Register 104: Interrupt Flags DAC & OCP/OTP Sticky Register - 0x00 / 0x00 / 0x68 (B0_P0_R104)
      25. 13.2.25Book 0 / Page 0 / Register 105-107: Reserved Registers - 0x00 / 0x00 / 0x69-0x6B (B0_P0_R105-R107)
      26. 13.2.26Book 0 / Page 0 / Register 108: DSP Interrupt Output Sticky Register - 0x00 / 0x00 / 0x6C (B0_P0_R108)
      27. 13.2.27Book 0 / Page 0 / Register 109-120: Reserved Registers - 0x00 / 0x00 / 0x6D-0x78 (B0_P0_R109-R120)
      28. 13.2.28Book 0 / Page 0 / Register 121: Power Modes Register - 0x00 / 0x00 / 0x79 (B0_P0_R121)
      29. 13.2.29Book 0 / Page 0 / Register 122-126: Reserved Registers - 0x00 / 0x00 / 0x7A-0x7E (B0_P0_R122-R126)
      30. 13.2.30Book 0 / Page 0 / Register 127: Book Selection Register - 0x00 / 0x00 / 0x7F (B0_P0_R127)
    3. 13.3 Book 0 Page 1
      1. 13.3.1 Book 0 / Page 1 / Register 0: Page Select Register - 0x00 / 0x01 / 0x00 (B0_P1_R0)
      2. 13.3.2 Book 0 / Page 1 / Register 1: ASI1 DAC Format Register - 0x00 / 0x01 / 0x01 (B0_P1_R1)
      3. 13.3.3 Book 0 / Page 1 / Register 2: ASI1 ADC Format Register - 0x00 / 0x01 / 0x02 (B0_P1_R2)
      4. 13.3.4 Book 0 / Page 1 / Register 3: ASI1 Offset Register - 0x00 / 0x00 / 0x03 (B0_P1_R3)
      5. 13.3.5 Book 0 / Page 1 / Register 4-6: Reserved Registers - 0x00 / 0x01 / 0x04-0x06 (B0_P1_R4-6)
      6. 13.3.6 Book 0 / Page 1 / Register 7: ASI1 ADC Path Register - 0x00 / 0x01 / 0x07 (B0_P1_R7)
      7. 13.3.7 Book 0 / Page 1 / Register 8: ASI1 DAC BCLK Register - 0x00 / 0x01 / 0x08 (B0_P1_R8)
      8. 13.3.8 Book 0 / Page 1 / Register 9: ASI1 DAC WCLK Register - 0x00 / 0x01 / 0x09 (B0_P1_R9)
      9. 13.3.9 Book 0 / Page 1 / Register 10: ASI1 ADC BCLK Register - 0x00 / 0x01 / 0x0A (B0_P1_R10)
      10. 13.3.10Book 0 / Page 1 / Register 11: ASI1 ADC WCLK Register - 0x00 / 0x01 / 0x0B (B0_P1_R11)
      11. 13.3.11Book 0 / Page 1 / Register 12: ASI1 DIN/DOUT MUX Register - 0x00 / 0x01 / 0x0C (B0_P1_R12)
      12. 13.3.12Book 0 / Page 1 / Register 13: ASI1 BDIV Clock Select Register - 0x00 / 0x01 / 0x0D (B0_P1_R13)
      13. 13.3.13Book 0 / Page 1 / Register 14: ASI1 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x0E (B0_P1_R14)
      14. 13.3.14Book 0 / Page 1 / Register 15: ASI1 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x0F (B0_P1_R15)
      15. 13.3.15Book 0 / Page 1 / Register 16: ASI1 DAC Clock Output Register - 0x00 / 0x01 / 0x10 (B0_P1_R16)
      16. 13.3.16Book 0 / Page 1 / Register 17: ASI1 ADC Clock Output Register - 0x00 / 0x01 / 0x11 (B0_P1_R17)
      17. 13.3.17Book 0 / Page 1 / Register 18-20: Reserved Registers - 0x00 / 0x01 / 0x12-0x14 (B0_P1_R18-20)
      18. 13.3.18Book 0 / Page 1 / Register 21: ASI2 DAC Format Register - 0x00 / 0x01 / 0x15 (B0_P1_R21)
      19. 13.3.19Book 0 / Page 1 / Register 22: ASI2 ADC Format Register - 0x00 / 0x01 / 0x16 (B0_P1_R22)
      20. 13.3.20Book 0 / Page 1 / Register 23: ASI2 Offset Register - 0x00 / 0x01 / 0x17 (B0_P1_R23)
      21. 13.3.21Book 0 / Page 1 / Register 24-26: Reserved Registers - 0x00 / 0x01 / 0x18-0x1A (B0_P1_R24-26)
      22. 13.3.22Book 0 / Page 1 / Register 27: ASI2 ADC Path Register - 0x00 / 0x01 / 0x1B (B0_P1_R27)
      23. 13.3.23Book 0 / Page 1 / Register 28: ASI2 DAC BCLK Register - 0x00 / 0x01 / 0x1C (B0_P1_R28)
      24. 13.3.24Book 0 / Page 1 / Register 29: ASI2 DAC WCLK Register - 0x00 / 0x01 / 0x1D (B0_P1_R29)
      25. 13.3.25Book 0 / Page 1 / Register 30: ASI2 ADC BCLK Register - 0x00 / 0x01 / 0x1E (B0_P1_R30)
      26. 13.3.26Book 0 / Page 1 / Register 31: ASI2 ADC WCLK Register - 0x00 / 0x01 / 0x1F (B0_P1_R31)
      27. 13.3.27Book 0 / Page 1 / Register 32: ASI2 DIN/DOUT MUX - 0x00 / 0x01 / 0x20 (B0_P1_R32)
      28. 13.3.28Book 0 / Page 1 / Register 33: ASI2 BDIV Clock Select Register - 0x00 / 0x01 / 0x21 (B0_P1_R33)
      29. 13.3.29Book 0 / Page 1 / Register 34: ASI2 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x22 (B0_P1_R34)
      30. 13.3.30Book 0 / Page 1 / Register 35: ASI2 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x23 (B0_P1_R35)
      31. 13.3.31Book 0 / Page 1 / Register 36: ASI2 DAC Clock Output Register - 0x00 / 0x01 / 0x24 (B0_P1_R36)
      32. 13.3.32Book 0 / Page 1 / Register 37: ASI2 ADC Clock Output Register - 0x00 / 0x01 / 0x25 (B0_P1_R37)
      33. 13.3.33Book 0 / Page 1 / Register 38-60: Reserved Registers - 0x00 / 0x01 / 0x26-0x3C (B0_P1_R38-60)
      34. 13.3.34Book 0 / Page 1 / Register 61: BCLK1_GPIO1 Pin Register - 0x00 / 0x01 / 0x3D (B0_P1_R61)
      35. 13.3.35Book 0 / Page 1 / Register 62: WCLK1_GPIO2 Pin Register - 0x00 / 0x01 / 0x3E (B0_P1_R62)
      36. 13.3.36Book 0 / Page 1 / Register 63: DOUT1_GPIO3 Pin Register - 0x00 / 0x01 / 0x3F (B0_P1_R63)
      37. 13.3.37Book 0 / Page 1 / Register 64: IRQ_GPIO4 Pin Register - 0x00 / 0x01 / 0x40 (B0_P1_R64)
      38. 13.3.38Book 0 / Page 1 / Register 65: BCLK2_GPIO5 Pin Register - 0x00 / 0x01 / 0x41 (B0_P1_R65)
      39. 13.3.39Book 0 / Page 1 / Register 66: WCLK2_GPIO6 Pin Register - 0x00 / 0x01 / 0x42 (B0_P1_R66)
      40. 13.3.40Book 0 / Page 1 / Register 67: DOUT2_GPIO7 Pin Register - 0x00 / 0x01 / 0x43 (B0_P1_R67)
      41. 13.3.41Book 0 / Page 1 / Register 68: DIN2_GPIO8 Pin Register - 0x00 / 0x01 / 0x44 (B0_P1_R68)
      42. 13.3.42Book 0 / Page 1 / Register 69: ICC_GPIO9 Pin(ICC_CLK) Register - 0x00 / 0x01 / 0x45 (B0_P1_R69)
      43. 13.3.43Book 0 / Page 1 / Register 70: ICC_GPIO10 Pin Register - 0x00 / 0x01 / 0x46 (B0_P1_R70)
      44. 13.3.44Book 0 / Page 1 / Register 71-76: Reserved Registers - 0x00 / 0x01 / 0x47-0x4C (B0_P1_R71-76)
      45. 13.3.45Book 0 / Page 1 / Register 77: GPI Pins Register - 0x00 / 0x01 / 0x4D (B0_P1_R77)
      46. 13.3.46Book 0 / Page 1 / Register 78: Reserved Register - 0x00 / 0x01 / 0x4E (B0_P1_R78)
      47. 13.3.47Book 0 / Page 1 / Register 79: GPIO HIZ CTRL1 Register - 0x00 / 0x01 / 0x4F (B0_P1_R79)
      48. 13.3.48Book 0 / Page 1 / Register 80: GPIO HIZ CTRL2 Register - 0x00 / 0x01 / 0x50 (B0_P1_R80)
      49. 13.3.49Book 0 / Page 1 / Register 81: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x51 (B0_P1_R81)
      50. 13.3.50Book 0 / Page 1 / Register 82: GPIO HIZ CTRL4 Register - 0x00 / 0x01 / 0x52 (B0_P1_R82)
      51. 13.3.51Book 0 / Page 1 / Register 83: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x53 (B0_P1_R83)
      52. 13.3.52Book 0 / Page 1 / Register 84-86: Reserved Registers - 0x00 / 0x01 / 0x54-0x56 (B0_P1_R84-86)
      53. 13.3.53Book 0 / Page 1 / Register 87: GPIO Pin 1 Register - 0x00 / 0x01 / 0x57 (B0_P1_R87)
      54. 13.3.54Book 0 / Page 1 / Register 88: GPIO Pin 2 Register - 0x00 / 0x01 / 0x58 (B0_P1_R88)
      55. 13.3.55Book 0 / Page 1 / Register 89: GPIO Pin 3 Register - 0x00 / 0x01 / 0x59 (B0_P1_R89)
      56. 13.3.56Book 0 / Page 1 / Register 90-107: Reserved Registers - 0x00 / 0x01 / 0x5A-0x6B (B0_P1_R84-86)
      57. 13.3.57Book 0 / Page 1 / Register 108: Interrupt Control 1 Register - 0x00 / 0x01 / 0x6C (B0_P1_R108)
      58. 13.3.58Book 0 / Page 1 / Register 109: Interrupt Control 2 Register - 0x00 / 0x01 / 0x6D (B0_P1_R109)
      59. 13.3.59Book 0 / Page 1 / Register 110: Interrupt Control 3 Register - 0x00 / 0x01 / 0x6E (B0_P1_R110)
      60. 13.3.60Book 0 / Page 1 / Register 111: Interrupt Control 4 Register - 0x00 / 0x01 / 0x6F (B0_P1_R111)
      61. 13.3.61Book 0 / Page 1 / Register 112: Interrupt Control 5 Register - 0x00 / 0x01 / 0x70 (B0_P1_R112)
      62. 13.3.62Book 0 / Page 1 / Register 113: Interrupt Control 6 Register - 0x00 / 0x01 / 0x71 (B0_P1_R113)
      63. 13.3.63Book 0 / Page 1 / Register 114-127: Reserved Register - 0x00 / 0x01 / 0x72-0x7F (B0_P1_R127)
    4. 13.4 Book 0 Page 2
      1. 13.4.1Book 0 / Page 2 / Register 0: Page Select Register - 0x00 / 0x02 / 0x00 (B0_P0_R0)
      2. 13.4.2Book 0 / Page 2 / Register 1-5: Reserved Register - 0x00 / 0x02 / 0x01-0x05 (B0_P1_R1-5)
      3. 13.4.3Book 0 / Page 2 / Register 6: Ramp Generator Frequency Register - 0x00 / 0x02 / 0x06 (B0_P2_R6)
      4. 13.4.4Book 0 / Page 2 / Register 7-23: Reserved Register - 0x00 / 0x02 / 0x07-0x17 (B0_P1_R7-23)
      5. 13.4.5Book 0 / Page 2 / Register 24: Inrush Optimization 1 Register - 0x00 / 0x02 / 0x18 (B0_P2_R24)
      6. 13.4.6Book 0 / Page 2 / Register 25: Inrush Optimization 2 Register - 0x00 / 0x02 / 0x19 (B0_P2_R25)
      7. 13.4.7Book 0 / Page 2 / Register 26: Inrush Optimization 3 Register - 0x00 / 0x02 / 0x1A (B0_P2_R25)
      8. 13.4.8Book 0 / Page 2 / Register 27: Inrush Optimization 4 Register - 0x00 / 0x02 / 0x1B (B0_P2_R25)
      9. 13.4.9Book 0 / Page 2 / Register 28-127: Reserved Register - 0x00 / 0x02 / 0x1C-0x7F (B0_P1_R28-127)
    5. 13.5 Book 100 Page 0
      1. 13.5.1 Book 100 / Page 0 / Register 0: Page Select Register - 0x64 / 0x00 / 0x00 (B100_P0_R0)
      2. 13.5.2 Book 100 / Page 0 / Register 1: DAC Interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
      3. 13.5.3 Book 100 / Page 0 / Register 2: ADC interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
      4. 13.5.4 Book 100 / Page 0 / Register 3-6: Reserved Register - 0x64 / 0x00 / 0x03-0x06 (B100_P0_R3-6)
      5. 13.5.5 Book 100 / Page 0 / Register 7: DSP Mute Register - 0x64 / 0x00 / 0x07 (B100_P0_R7)
      6. 13.5.6 Book 100 / Page 0 / Register 8-15: Reserved Register - 0x64 / 0x00 / 0x08-0x0F (B100_P0_R8-15)
      7. 13.5.7 Book 100 / Page 0 / Register 16: Interrupt 1 DSP Register - 0x64 / 0x00 / 0x10 (B100_P0_R16)
      8. 13.5.8 Book 100 / Page 0/ Register 17: Interrupt 2 DSP Register - 0x64 / 0x00 / 0x11 (B100_P0_R17)
      9. 13.5.9 Book 100 / Page 0 / Register 18: Condition 1 DSP Register - 0x64 / 0x00 / 0x12 (B100_P0_R18)
      10. 13.5.10Book 100/ Page 0 / Register 19: Condition 2 DSP Register - 0x64 / 0x00 / 0x13 (B100_P0_R19)
      11. 13.5.11Book 100 / Page 0 / Register 20: ISR and COND Control Register - 0x64 / 0x00 / 0x14 (B100_P0_R20)
      12. 13.5.12Book 100 / Page 0/ Register 21: DSP Control Register - 0x64 / 0x00 / 0x15 (B100_P0_R21)
      13. 13.5.13Book 100 / Page 0 / Register 22-26: Reserved Register - 0x64 / 0x00 / 0x16-0x1A (B100_P0_R22-26)
      14. 13.5.14Book 100 / Page 0 / Register 27:PLL CLKIN Divider Register - 0x64 / 0x00 / 0x1B (B100_P0_R27)
      15. 13.5.15Book 100 / Page 0 / Register 28:PLL J-VAL Divider Register - 0x64 / 0x00 / 0x1C (B100_P0_R28)
      16. 13.5.16Book 100 / Page 0 / Register 29:PLL D-VAL Divider 2 Register - 0x64 / 0x00 / 0x1D (B100_P0_R29)
      17. 13.5.17Book 100 / Page 0 / Register 30:PLL D-VAL Divider 1 Register - 0x64 / 0x00 / 0x1E (B100_P0_R30)
      18. 13.5.18Book 100 / Page 0 / Register 31:DSP Clock Register - 0x64 / 0x00 / 0x1F (B100_P0_R31)
      19. 13.5.19Book 100 / Page 0 / Register 32: N-VAL Divider Register - 0x64 / 0x00 / 0x20 (B100_P0_R32)
      20. 13.5.20Book 100 / Page 0 / Register 33: MDAC-VAL Divider Register - 0x64 / 0x00 / 0x21 (B100_P0_R33)
      21. 13.5.21Book 100 / Page 0 / Register 34: MADC-VAL Divider Register - 0x64 / 0x00 / 0x22 (B100_P0_R34)
      22. 13.5.22Book 100 / Page 0 / Register 35-37: Reserved Register - 0x64 / 0x00 / 0x23-0x25 (B100_P0_R35-37)
      23. 13.5.23Book 100 / Page 0 / Register 38: Charge-pump Clock Register - 0x64 / 0x00 / 0x26 (B100_P0_R38)
      24. 13.5.24Book 100 / Page 0 / Register 39: Boost Clock Register - 0x64 / 0x00 / 0x27 (B100_P0_R39)
      25. 13.5.25Book 100 / Page 0 / Register 40: Ramp Clock 1 Register - 0x64 / 0x00 / 0x28 (B100_P0_R40)
      26. 13.5.26Book 100 / Page 0 / Register 41-42: Reserved Register - 0x64 / 0x00 / 0x29-0x2A (B100_P0_R41-42)
      27. 13.5.27Book 100 / Page 0 / Register 43: Ramp Clock 2 Register - 0x64 / 0x00 / 0x2B (B100_P0_R43)
      28. 13.5.28Book 100 / Page 0 / Register 44: Ramp Clock 3 Register - 0x64 / 0x00 / 0x2C (B100_P0_R44)
      29. 13.5.29Book 100 / Page 0/ Register 45-126: Reserved Register - 0x64 / 0x01 / 0x2D-0x7E (B100_P0_R45-126)
      30. 13.5.30Book 100 / Page 0 / Register 127: Book Selection Register - 0x64 / 0x00 / 0x7F (B100_P0_R127)
  14. 14器件和文档支持
    1. 14.1文档支持
    2. 14.2社区资源
    3. 14.3商标
    4. 14.4静电放电警告
    5. 14.5Glossary
  15. 15机械、封装和可订购信息
    1. 15.1封装尺寸

Specifications

Absolute Maximum Ratings

over operating free-air temperature range, TA = 25°C (unless otherwise noted)(1)
MINMAXUNIT
Battery voltageVBAT–0.36V
Analog supply voltageAVDD–0.32V
Digital supply voltageDVDD–0.32V
I/O Supply voltageIOVDD–0.33.9V
Analog input voltageIN_M, IN_P–0.3AVDD V
Digital input voltage–0.3IOVDD + 0.3V
Output continuous total power dissipationSee Thermal InformationNA
Storage temperature, Tstg –65150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Procedures is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±2500V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
Battery voltageVBAT2.9(1)3.65.5V
Analog supply voltageAVDD1.651.81.95V
Digital supply voltageDVDD1.651.81.95V
I/O supply voltage 1.8VIOVDD1.621.81.98V
I/O supply voltage 3.3VIOVDD3.03.33.6V
TAOperating free-air temperature–4085°C
TJOperating junction temperature–40150°C
Device is functional down to 2.7V. See Battery Tracking AGC

Thermal Information

THERMAL METRIC(1)TAS2555UNIT
42 PINS
RθJAJunction-to-ambient thermal resistance 49.8°C/W
RθJC(top)Junction-to-case (top) thermal resistance 0.2
RθJBJunction-to-board thermal resistance 7.1
ψJTJunction-to-top characterization parameter 0.8
ψJBJunction-to-board characterization parameter 7.1
RθJC(bot)Junction-to-case (bottom) thermal resistance n/a
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Electrical Characteristics

VBAT = 3.6V, AVDD = DVDD = IOVDD = 1.8 V, RESET = IOVDD, Gain = 16.4 dB, ERC = 14ns, Boost Inductor = 2.2 µH, RL = 8 Ω + 33 µH, 1-kHz input frequency, 48- kHz sample rate for digital input, Class-H Boost Enabled, TA= 25°C, ILIM = 3 A (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
BOOST CONVERTER
Boost Output VoltageAverage voltage (w/o including ripple). 8.5V
Boost Converter Switching Frequency1.77MHz
Boost Converter Current Limit3A
Boost Converter Max In-Rush CurrentHigh Efficiency Mode: Max inductor inrush and startup current after enable4A
Normal Efficiency Mode: Max inductor inrush and startup current after enable1.5
CLASS-D CHANNEL
Output Voltage for Full-Scale Digital Input6.6VRMS
Load Resistance (Load Spec Resistance)3.68Ω
Class-D Frequency Avg Frequency in Spread-Spectrum Mode384kHz
Fixed Frequency44.1 × 848 × 8
Class-D + Boost Efficiency POUT = 3.5 W (sinewave) ROM Mode 180%
POUT = 0.5 W (sinewave) ROM Mode 187
Class-D Output Current Limit (Short Circuit Protection) VBOOST = 8.5 V, OUT– shorted to VBAT, VBOOST, GND 6A
Class-D Output Offset Voltage in Digital Input Mode –2.52.5mV
Programmable Channel Gain Accuracy±0.5dB
Mute Attenuation Device in shutdown or device in normal operation and MUTED150dB
VBAT Power Supply Rejection Ratio (PSRR)Ripple of 200 mVpp at 217 Hz110dB
AVDD Power Supply Rejection Ratio (PSRR) Ripple of 200 mVpp at 217 Hz99dB
THD+N 1 kHz, POUT = 0.1 W0.0041%
1 kHz, Po = 0.5 W0.0036
1 kHz, Po = 1 W0.0035
1 kHz, Po = 3 W0.02
Output Integrated Noise (20 Hz-20 kHz) - 8 Ω A-wt Filter, DAC modulator switching 15.9µV
Signal-to-noise ratioReferenced to 1% THD+N at output, a-weighted110.6dB
Max Output Power, 3-A Current LimitTHD+N=1%, 8-Ω Load3.7W
THD+N=1%, 6-Ω Load4.5
THD+N=1%, 4-Ω Load5
Startup PopDigital Input, A-weighted output10mV
Output Impedance in Shutdown /RESET = 0 V 10
Startup Time Time taken from end of configuring device in ROM mode1/2 to Speaker output signal in SPI mode running at 25 MHz with 48 ksps input 8mS
Shutdown Time Measured from time when device is programmed in software shutdown mode 100µS
CURRENT SENSE
Current Sense Full ScalePeak current which will give full scale digital output 8-Ω load1.25APEAK
Peak current which will give full scale digital output 6-Ω load1.48
Peak current which will give full scale digital output 4-Ω load1.76
Current Sense AccuracyIOUT = 354 mARMS (1 W)1%
VOLTAGE SENSE
Voltage Sense Full ScalePeak voltage which will give full scale digital output 8.5VPEAK
Voltage Sense AccuracyVOUT = 2.83 Vrms (1 W) 1%
INTERFACE
Voltage and Current Sense Data Rate TDM/I2S 48kHz
Voltage and Current Sense ADC OSR TDM/I2S 64OSR
FMCLKMCLK frequency0.51249.15MHz
POWER CONSUMPTION
Power Consumption with Digital Input and Speaker Protection Disabled (ROM MODE 1)From VBAT, PLL off, no signal 3mA
From AVDD, PLL off, no signal 1.7mA
From DVDD, PLL off, no signal 3.9mA
Power Consumption with Digital Input and Speaker Protection Enabled From VBAT, PLL on, no signal 3mA
From AVDD, PLL on, no signal 3.4mA
From DVDD, PLL on, no signal 20mA
Power Consumption in Hardware Shutdown From VBAT, /RESET = 0 0.1µA
From AVDD, /RESET = 0 0.2µA
From DVDD, /RESET = 0 1µA
Power Consumption in Software Shutdown See Low Power Sleep ModeFrom VBAT0.1µA
From AVDD 0.1µA
From DVDD 9.7µA
DIGITAL INPUT / OUTPUT
VIHHigh-level digital input voltageAll digital pins except SDA and SCL, IOVDD = 1.8-V operation0.65 × IOVDD V
VIL Low-level digital input voltage0.35 × IOVDDV
VIHHigh-level digital input voltageAll digital pins except SDA and SCL, IOVDD = 3.3-V operation2 V
VIL Low-level digital input voltage0.45V
VOH High-level digital output voltageAll digital pins except SDA and SCL, IOVDD = 1.8-V operation For IOL = 2 mA and IOH = –2 mA IOVDD – 0.45V
VOL Low-level digital output voltage0.45 V
VOH High-level digital output voltageAll digital pins except SDA and SCL, IOVDD = 3.3-V operation For IOL = 2 mA and IOH = –2 mA 2.4V
VOL Low-level digital output voltage0.4 V
IIH High-level digital input leakage currentInput = IOVDD –50.15 µA
IIL Low-level digital input leakage currentInput = Ground –50.15 µA
MISCELLANEOUS
TTRIP Thermal Trip Point140°C

I2C Timing Requirements

For I2C interface signals over recommended operating conditions (unless otherwise noted). Note: All timing specifications are specified by design but not tested at final test. See Figure 1
PARAMETERTEST CONDITIONStandard-ModeFast-ModeUNITS
MINTYPMAXMINTYPMAX
fSCL SCL clock frequency01000400kHz
tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated.40.6μs
tLOW LOW period of the SCL clock 4.71.3μs
tHIGH HIGH period of the SCL clock40.6μs
tSU;STA Setup time for a repeated START condition 4.70.6μs
tHD;DAT Data hold time: For I2C bus devices 03.4500.9μs
tSU;DAT Data set-up time250100ns
tr SDA and SCL Rise Time100020 + 0.1 × Cb300ns
tf SDA and SCL Fall Time30020 + 0.1 × Cb300ns
tSU;STO Set-up time for STOP condition40.6μs
tBUF Bus free time between a STOP and START condition4.71.3μs
Cb Capacitive load for each bus line 400400pF

SPI Timing Requirements

For SPI interface signals over recommended operating conditions (unless otherwise noted). Note: All timing specifications are specified by design but not tested at final test. See Figure 2
PARAMETERTEST CONDITIONIOVDD = 1.8 VIOVDD = 3.3 VUNITS
MINTYPMAXMINTYPMAX
tsck SCLK Period4030ns
tsckh SCLK Pulse width High4030ns
tsckl SCLK Pulse width Low4030ns
tlead Enable Lead Time4030ns
ttrail Enable Trail Time4030ns
td;seqxfr Sequential Transfer Delay4030ns
ta Slave DOUT access time 3525ns
tdis Slave DOUT disable time3525ns
tsu DIN data setup time88ns
th;DIN DIN data hold time88ns
tv;DOUT DOUT data valid time3525ns
tr SCLK Rise Time44ns
tf SCLK Fall Time44ns

I2S/LJF/RJF Timing in Master Mode

All specifications at TA = –40°C to 85°C, IOVDD data sheet limits, VIL and VIH applied, VOL and VOH measured at datasheet limits, lumped capacitive load of 20 pF on output pins unless otherwise noted. See Figure 3(1)
SYMBOLPARAMETERCONDITIONSIOVDD = 1.8 VIOVDD = 3.3 VUNIT
MINMAXMINMAX
td(WS)BCLK to WCLK delay50% of BCLK to 50% of WCLK3525ns
td(DO-WS)WCLK to DOUT delay (For LJF Mode only)50% of WCLK to 50% of DOUT3525ns
td(DO-BCLK)BCLK to DOUT delay50% of BCLK to 50% of DOUT3525ns
ts(DI)DIN setup88ns
th(DI)DIN hold88ns
trRise time10%-90% Rise Time84ns
tfFall time90%-10% Fall Time84ns
All timing specifications are measured at characterization but not tested at final test.

I2S/LJF/RJF Timing in Slave Mode

All specifications at TA = –40°C to 85°C, IOVDD data sheet limits, VIL and VIH applied, VOL and VOH measured at datasheet limits, lumped capacitive load of 20 pF on output pins unless otherwise noted. See Figure 4(1)
SYMBOLPARAMETERCONDITIONSIOVDD = 1.8 VIOVDD = 3.3 VUNIT
MINMAXMINMAX
tH(BCLK)BCLK high period4030ns
tL(BCLK)BCLK low period4030ns
ts(WS)(WS)88ns
th(WS)WCLK hold88ns
td(DO-WS)WCLK to DOUT delay (For LJF Mode only)50% of WCLK to 50% of DOUT3525ns
td(DO-BCLK)BCLK to DOUT delay50% of BCLK to 50% of DOUT3525ns
ts(DI)DIN setup88ns
th(DI)DIN hold88ns
trRise time10%-90% Rise Time84ns
tf Fall time90%-10% Fall Time84ns

DSP Timing in Master Mode

All specifications at TA = –40°C to 85°C, IOVDD data sheet limits, VIL and VIH applied, VOL and VOH measured at datasheet limits, lumped capacitive load of 20 pF on output pins unless otherwise noted. See Figure 5
SYMBOLPARAMETERCONDITIONSIOVDD = 1.8 VIOVDD = 3.3 VUNIT
MINMAXMINMAX
td(WS)BCLK to WCLK delay50% of BCLK to 50% of WCLK3525ns
td(DO-BCLK)BCLK to DOUT delay50% of BLCK to 50% of DOUT3525ns
ts(DI)DIN setup88ns
th(DI)DIN hold88ns
trRise time10%-90% Rise Time84ns
tfFall time90%-10% Fall Time84ns

DSP Timing in Slave Mode

All specifications at 25°C, IOVDD = 1.8 V Ssee Figure 6(1)
SYMBOLPARAMETERCONDITIONSIOVDD=1.8VIOVDD=3.3VUNIT
MINMAXMINMAX
tH(BCLK)BCLK high period4030ns
tL(BCLK)BCLK low period4030ns
ts(WS)WCLK seutp88ns
th(WS)WCLK hold88ns
td(DO-BCLK)BCLK to DOUT delay (For LJF Mode only)50% BCLK to 50% DOUT3525ns
ts(DI)DIN setup88ns
th(DI)DIN hold88ns
trRise time10%-90% Rise Time84ns
tfFall time90%-10% Fall Time84ns
TAS2555 i2c_timing.gif Figure 1. I2C Timing
TAS2555 if_tim_los585.gif Figure 2. SPI Interface Timing Diagram
TAS2555 master_tim_los585.gif Figure 3. I2S/LJF/RJF Timing in Master Mode
TAS2555 i2sljfrlf_los585.gif Figure 4. I2S/LJF/RJF Timing in Slave Mode
TAS2555 dsp_tim_los585.gif Figure 5. DSP Timing in Master Mode
TAS2555 dsp_slave_los585.gif Figure 6. DSP Timing in Slave Mode

Typical Characteristics

VBAT = 3.6 V, AVDD = IOVDD = 1.8 V, RESET = IOVDD, RL = 8 Ω + 33 µH, I2S digital input, ROM mode 1 (unless otherwise noted).
TAS2555 D001_SLASE69_TAS2555.gif
8 Ω + 33 µH Freq = 1 kHz
Figure 7. THD+N vs Output Power
TAS2555 D003_SLASE69_TAS2555.gif
4 Ω + 16 µHFreq = 1 kHz
Figure 9. THD+N vs Output Power
TAS2555 D005_SLASE69_TAS2555.gif
8 Ω + 33 µH POUT = 1 W
Figure 11. THD+N vs Frequency
TAS2555 D007_SLASE69_TAS2555.gif
Figure 13. VBAT Supply Ripple Rejection vs Frequency
TAS2555 D009_SLASE69_TAS2555.gif
8 Ω + 33 µH
Figure 15. Efficiency vs Output Power
TAS2555 D002_SLASE69_TAS2555.gif
8 Ω + 33 µHFreq = 6.6 kHz
Figure 8. THD+N vs Output Power
TAS2555 D004_SLASE69_TAS2555.gif
4 Ω + 16 µHFreq = 6.6 kHz
Figure 10. THD+N vs Output Power
TAS2555 D006_SLASE69_TAS2555.gif
4 Ω + 16 µHPOUT = 1 W
Figure 12. THD+N vs Frequency
TAS2555 D008_SLASE69_TAS2555.gif
Figure 14. AVDD Supply Ripple Rejection vs Frequency
TAS2555 D010_SLASE69_TAS2555.gif
4 Ω + 16 µH
Figure 16. Efficiency vs Output Power