ZHCSFY2A August 2015  – November 2016 TAS2555

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 SPI Timing Requirements
    8. 7.8 I2S/LJF/RJF Timing in Master Mode
    9. 7.9 I2S/LJF/RJF Timing in Slave Mode
    10. 7.10DSP Timing in Master Mode
    11. 7.11DSP Timing in Slave Mode
    12. 7.12Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1 General I2C Operation
      2. 9.3.2 Single-Byte and Multiple-Byte Transfers
      3. 9.3.3 Single-Byte Write
      4. 9.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.3.5 Single-Byte Read
      6. 9.3.6 Multiple-Byte Read
      7. 9.3.7 General SPI Operation
      8. 9.3.8 Class-D Edge Rate Control
      9. 9.3.9 Battery Tracking AGC
      10. 9.3.10Configurable Boost Current Limit (ILIM)
        1. 9.3.10.1Fault Protection
          1. 9.3.10.1.1OverCurrent
          2. 9.3.10.1.2Analog Undervoltage
          3. 9.3.10.1.3Overtemperature
          4. 9.3.10.1.4Clocking Faults
        2. 9.3.10.2Brownout
        3. 9.3.10.3Spread Spectrum vs Synchronized
        4. 9.3.10.4IRQs and Flags
        5. 9.3.10.5Software Reset
        6. 9.3.10.6PurePath Console 3 Software TAS2555 Application
    4. 9.4Device Functional Modes
      1. 9.4.1Audio Digital I/O Interface
        1. 9.4.1.1Right-Justified Mode (RJF)
        2. 9.4.1.2Left-Justified Mode (LJF)
        3. 9.4.1.3I2S Mode
        4. 9.4.1.4DSP Mode
      2. 9.4.2TDM Mode
      3. 9.4.3Device Digital Processing Modes
        1. 9.4.3.1ROM Mode 1
        2. 9.4.3.2ROM Mode 2
        3. 9.4.3.3SmartAmp Mode
      4. 9.4.4Low Power Sleep Mode
    5. 9.5Programming
      1. 9.5.1Code Loading and CRC check
      2. 9.5.2Device Power Up, Power Down, Mute and Un-mute Sequence
  10. 10Applications and Implementation
    1. 10.1Application Information
    2. 10.2Typical Applications
      1. 10.2.1Design Requirements
        1. 10.2.1.1Detailed Design Procedure
          1. 10.2.1.1.1Mono/Stereo Configuration
          2. 10.2.1.1.2Boost Converter Passive Devices
          3. 10.2.1.1.3EMI Passive Devices
          4. 10.2.1.1.4Miscellaneous Passive Devices
      2. 10.2.2Application Performance Plots
    3. 10.3Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1Power Supplies
    2. 11.2Power Supply Sequencing
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Register Map
    1. 13.1Register Map Summary
    2. 13.2 Book 0 Page 0
      1. 13.2.1 Book 0 / Page 0 / Register 0: Page Select Register - 0x00 / 0x00 / 0x00 (B0_P0_R0)
      2. 13.2.2 Book 0 / Page 0 / Register 1: Software Reset Register - 0x00 / 0x00 / 0x01 (B0_P0_R1)
      3. 13.2.3 Book 0 / Page 0 / Register 2-3: Reserved Registers - 0x00 / 0x00 / 0x02-0x03 (B0_P0_R2-3)
      4. 13.2.4 Book 0 / Page 0 / Register 4: Power Control Register - 0x00 / 0x00 / 0x04 (B0_P0_R4)
      5. 13.2.5 Book 0 / Page 0 / Register 5: Power Control Register 2 - 0x00 / 0x00 / 0x05 (B0_P0_R5)
      6. 13.2.6 Book 0 / Page 0 / Register 6: Speaker Control Register - 0x00 / 0x00 / 0x06 (B0_P0_R6)
      7. 13.2.7 Book 0 / Page 0 / Register 7: Mute Register - 0x00 / 0x00 / 0x07 (B0_P0_R7)
      8. 13.2.8 Book 0 / Page 0 / Register 8: Channel Control Register - 0x00 / 0x00 / 0x08 (B0_P0_R8)
      9. 13.2.9 Book 0 / Page 0 / Register 9-31: Reserved Registers - 0x00 / 0x00 / 0x09-0x1F (B0_P0_R9-31)
      10. 13.2.10Book 0 / Page 0 / Register 32: CRC Checksum Register - 0x00 / 0x00 / 0x20 (B0_P0_R32)
      11. 13.2.11Book 0 / Page 0 / Register 33: Checksum Reset Register - 0x00 / 0x00 / 0x21 (B0_P0_R33)
      12. 13.2.12Book 0 / Page 0 / Register 34: Device DSP Mode Register - 0x00 / 0x00 / 0x22 (B0_P0_R34)
      13. 13.2.13Book 0 / Page 0 / Register 35-39: Reserved Registers - 0x00 / 0x00 / 0x23-0x27 (B0_P0_R35-R39)
      14. 13.2.14Book 0 / Page 0 / Register 40: Class-D SSM Mode Register - 0x00 / 0x00 / 0x28 (B0_P0_R40)
      15. 13.2.15Book 0 / Page 0 / Register 41: Reserved Registers - 0x00 / 0x00 / 0x29 (B0_P0_R41)
      16. 13.2.16Book 0 / Page 0 / Register 42: Digital Playback Control Register - 0x00 / 0x00 / 0x2A (B0_P0_R42)
      17. 13.2.17Book 0 / Page 0 / Register 43: Current Limit Register - 0x00 / 0x00 / 0x2B (B0_P0_R43)
      18. 13.2.18Book 0 / Page 0 / Register 44: Clock Error Control 1 Register - 0x00 / 0x00 / 0x2C (B0_P0_R44)
      19. 13.2.19Book 0 / Page 0 / Register 45: Clock Error Control 2 Register - 0x00 / 0x00 / 0x2D (B0_P0_R45)
      20. 13.2.20Book 0 / Page 0 / Register 46: Clock Error Control 3 Register - 0x00 / 0x00 / 0x2E (B0_P0_R46)
      21. 13.2.21Book 0 / Page 0 / Register 47-99: Reserved Registers - 0x00 / 0x00 / 0x2F-0x63 (B0_P0_R47-R99)
      22. 13.2.22Book 0 / Page 0 / Register 100: Power Up Flag Register - 0x00 / 0x00 / 0x64 (B0_P0_R100)
      23. 13.2.23Book 0 / Page 0 / Register 101-103: Reserved Registers - 0x00 / 0x00 / 0x65-0x67 (B0_P0_R101-R103)
      24. 13.2.24Book 0 / Page 0 / Register 104: Interrupt Flags DAC & OCP/OTP Sticky Register - 0x00 / 0x00 / 0x68 (B0_P0_R104)
      25. 13.2.25Book 0 / Page 0 / Register 105-107: Reserved Registers - 0x00 / 0x00 / 0x69-0x6B (B0_P0_R105-R107)
      26. 13.2.26Book 0 / Page 0 / Register 108: DSP Interrupt Output Sticky Register - 0x00 / 0x00 / 0x6C (B0_P0_R108)
      27. 13.2.27Book 0 / Page 0 / Register 109-120: Reserved Registers - 0x00 / 0x00 / 0x6D-0x78 (B0_P0_R109-R120)
      28. 13.2.28Book 0 / Page 0 / Register 121: Power Modes Register - 0x00 / 0x00 / 0x79 (B0_P0_R121)
      29. 13.2.29Book 0 / Page 0 / Register 122-126: Reserved Registers - 0x00 / 0x00 / 0x7A-0x7E (B0_P0_R122-R126)
      30. 13.2.30Book 0 / Page 0 / Register 127: Book Selection Register - 0x00 / 0x00 / 0x7F (B0_P0_R127)
    3. 13.3 Book 0 Page 1
      1. 13.3.1 Book 0 / Page 1 / Register 0: Page Select Register - 0x00 / 0x01 / 0x00 (B0_P1_R0)
      2. 13.3.2 Book 0 / Page 1 / Register 1: ASI1 DAC Format Register - 0x00 / 0x01 / 0x01 (B0_P1_R1)
      3. 13.3.3 Book 0 / Page 1 / Register 2: ASI1 ADC Format Register - 0x00 / 0x01 / 0x02 (B0_P1_R2)
      4. 13.3.4 Book 0 / Page 1 / Register 3: ASI1 Offset Register - 0x00 / 0x00 / 0x03 (B0_P1_R3)
      5. 13.3.5 Book 0 / Page 1 / Register 4-6: Reserved Registers - 0x00 / 0x01 / 0x04-0x06 (B0_P1_R4-6)
      6. 13.3.6 Book 0 / Page 1 / Register 7: ASI1 ADC Path Register - 0x00 / 0x01 / 0x07 (B0_P1_R7)
      7. 13.3.7 Book 0 / Page 1 / Register 8: ASI1 DAC BCLK Register - 0x00 / 0x01 / 0x08 (B0_P1_R8)
      8. 13.3.8 Book 0 / Page 1 / Register 9: ASI1 DAC WCLK Register - 0x00 / 0x01 / 0x09 (B0_P1_R9)
      9. 13.3.9 Book 0 / Page 1 / Register 10: ASI1 ADC BCLK Register - 0x00 / 0x01 / 0x0A (B0_P1_R10)
      10. 13.3.10Book 0 / Page 1 / Register 11: ASI1 ADC WCLK Register - 0x00 / 0x01 / 0x0B (B0_P1_R11)
      11. 13.3.11Book 0 / Page 1 / Register 12: ASI1 DIN/DOUT MUX Register - 0x00 / 0x01 / 0x0C (B0_P1_R12)
      12. 13.3.12Book 0 / Page 1 / Register 13: ASI1 BDIV Clock Select Register - 0x00 / 0x01 / 0x0D (B0_P1_R13)
      13. 13.3.13Book 0 / Page 1 / Register 14: ASI1 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x0E (B0_P1_R14)
      14. 13.3.14Book 0 / Page 1 / Register 15: ASI1 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x0F (B0_P1_R15)
      15. 13.3.15Book 0 / Page 1 / Register 16: ASI1 DAC Clock Output Register - 0x00 / 0x01 / 0x10 (B0_P1_R16)
      16. 13.3.16Book 0 / Page 1 / Register 17: ASI1 ADC Clock Output Register - 0x00 / 0x01 / 0x11 (B0_P1_R17)
      17. 13.3.17Book 0 / Page 1 / Register 18-20: Reserved Registers - 0x00 / 0x01 / 0x12-0x14 (B0_P1_R18-20)
      18. 13.3.18Book 0 / Page 1 / Register 21: ASI2 DAC Format Register - 0x00 / 0x01 / 0x15 (B0_P1_R21)
      19. 13.3.19Book 0 / Page 1 / Register 22: ASI2 ADC Format Register - 0x00 / 0x01 / 0x16 (B0_P1_R22)
      20. 13.3.20Book 0 / Page 1 / Register 23: ASI2 Offset Register - 0x00 / 0x01 / 0x17 (B0_P1_R23)
      21. 13.3.21Book 0 / Page 1 / Register 24-26: Reserved Registers - 0x00 / 0x01 / 0x18-0x1A (B0_P1_R24-26)
      22. 13.3.22Book 0 / Page 1 / Register 27: ASI2 ADC Path Register - 0x00 / 0x01 / 0x1B (B0_P1_R27)
      23. 13.3.23Book 0 / Page 1 / Register 28: ASI2 DAC BCLK Register - 0x00 / 0x01 / 0x1C (B0_P1_R28)
      24. 13.3.24Book 0 / Page 1 / Register 29: ASI2 DAC WCLK Register - 0x00 / 0x01 / 0x1D (B0_P1_R29)
      25. 13.3.25Book 0 / Page 1 / Register 30: ASI2 ADC BCLK Register - 0x00 / 0x01 / 0x1E (B0_P1_R30)
      26. 13.3.26Book 0 / Page 1 / Register 31: ASI2 ADC WCLK Register - 0x00 / 0x01 / 0x1F (B0_P1_R31)
      27. 13.3.27Book 0 / Page 1 / Register 32: ASI2 DIN/DOUT MUX - 0x00 / 0x01 / 0x20 (B0_P1_R32)
      28. 13.3.28Book 0 / Page 1 / Register 33: ASI2 BDIV Clock Select Register - 0x00 / 0x01 / 0x21 (B0_P1_R33)
      29. 13.3.29Book 0 / Page 1 / Register 34: ASI2 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x22 (B0_P1_R34)
      30. 13.3.30Book 0 / Page 1 / Register 35: ASI2 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x23 (B0_P1_R35)
      31. 13.3.31Book 0 / Page 1 / Register 36: ASI2 DAC Clock Output Register - 0x00 / 0x01 / 0x24 (B0_P1_R36)
      32. 13.3.32Book 0 / Page 1 / Register 37: ASI2 ADC Clock Output Register - 0x00 / 0x01 / 0x25 (B0_P1_R37)
      33. 13.3.33Book 0 / Page 1 / Register 38-60: Reserved Registers - 0x00 / 0x01 / 0x26-0x3C (B0_P1_R38-60)
      34. 13.3.34Book 0 / Page 1 / Register 61: BCLK1_GPIO1 Pin Register - 0x00 / 0x01 / 0x3D (B0_P1_R61)
      35. 13.3.35Book 0 / Page 1 / Register 62: WCLK1_GPIO2 Pin Register - 0x00 / 0x01 / 0x3E (B0_P1_R62)
      36. 13.3.36Book 0 / Page 1 / Register 63: DOUT1_GPIO3 Pin Register - 0x00 / 0x01 / 0x3F (B0_P1_R63)
      37. 13.3.37Book 0 / Page 1 / Register 64: IRQ_GPIO4 Pin Register - 0x00 / 0x01 / 0x40 (B0_P1_R64)
      38. 13.3.38Book 0 / Page 1 / Register 65: BCLK2_GPIO5 Pin Register - 0x00 / 0x01 / 0x41 (B0_P1_R65)
      39. 13.3.39Book 0 / Page 1 / Register 66: WCLK2_GPIO6 Pin Register - 0x00 / 0x01 / 0x42 (B0_P1_R66)
      40. 13.3.40Book 0 / Page 1 / Register 67: DOUT2_GPIO7 Pin Register - 0x00 / 0x01 / 0x43 (B0_P1_R67)
      41. 13.3.41Book 0 / Page 1 / Register 68: DIN2_GPIO8 Pin Register - 0x00 / 0x01 / 0x44 (B0_P1_R68)
      42. 13.3.42Book 0 / Page 1 / Register 69: ICC_GPIO9 Pin(ICC_CLK) Register - 0x00 / 0x01 / 0x45 (B0_P1_R69)
      43. 13.3.43Book 0 / Page 1 / Register 70: ICC_GPIO10 Pin Register - 0x00 / 0x01 / 0x46 (B0_P1_R70)
      44. 13.3.44Book 0 / Page 1 / Register 71-76: Reserved Registers - 0x00 / 0x01 / 0x47-0x4C (B0_P1_R71-76)
      45. 13.3.45Book 0 / Page 1 / Register 77: GPI Pins Register - 0x00 / 0x01 / 0x4D (B0_P1_R77)
      46. 13.3.46Book 0 / Page 1 / Register 78: Reserved Register - 0x00 / 0x01 / 0x4E (B0_P1_R78)
      47. 13.3.47Book 0 / Page 1 / Register 79: GPIO HIZ CTRL1 Register - 0x00 / 0x01 / 0x4F (B0_P1_R79)
      48. 13.3.48Book 0 / Page 1 / Register 80: GPIO HIZ CTRL2 Register - 0x00 / 0x01 / 0x50 (B0_P1_R80)
      49. 13.3.49Book 0 / Page 1 / Register 81: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x51 (B0_P1_R81)
      50. 13.3.50Book 0 / Page 1 / Register 82: GPIO HIZ CTRL4 Register - 0x00 / 0x01 / 0x52 (B0_P1_R82)
      51. 13.3.51Book 0 / Page 1 / Register 83: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x53 (B0_P1_R83)
      52. 13.3.52Book 0 / Page 1 / Register 84-86: Reserved Registers - 0x00 / 0x01 / 0x54-0x56 (B0_P1_R84-86)
      53. 13.3.53Book 0 / Page 1 / Register 87: GPIO Pin 1 Register - 0x00 / 0x01 / 0x57 (B0_P1_R87)
      54. 13.3.54Book 0 / Page 1 / Register 88: GPIO Pin 2 Register - 0x00 / 0x01 / 0x58 (B0_P1_R88)
      55. 13.3.55Book 0 / Page 1 / Register 89: GPIO Pin 3 Register - 0x00 / 0x01 / 0x59 (B0_P1_R89)
      56. 13.3.56Book 0 / Page 1 / Register 90-107: Reserved Registers - 0x00 / 0x01 / 0x5A-0x6B (B0_P1_R84-86)
      57. 13.3.57Book 0 / Page 1 / Register 108: Interrupt Control 1 Register - 0x00 / 0x01 / 0x6C (B0_P1_R108)
      58. 13.3.58Book 0 / Page 1 / Register 109: Interrupt Control 2 Register - 0x00 / 0x01 / 0x6D (B0_P1_R109)
      59. 13.3.59Book 0 / Page 1 / Register 110: Interrupt Control 3 Register - 0x00 / 0x01 / 0x6E (B0_P1_R110)
      60. 13.3.60Book 0 / Page 1 / Register 111: Interrupt Control 4 Register - 0x00 / 0x01 / 0x6F (B0_P1_R111)
      61. 13.3.61Book 0 / Page 1 / Register 112: Interrupt Control 5 Register - 0x00 / 0x01 / 0x70 (B0_P1_R112)
      62. 13.3.62Book 0 / Page 1 / Register 113: Interrupt Control 6 Register - 0x00 / 0x01 / 0x71 (B0_P1_R113)
      63. 13.3.63Book 0 / Page 1 / Register 114-127: Reserved Register - 0x00 / 0x01 / 0x72-0x7F (B0_P1_R127)
    4. 13.4 Book 0 Page 2
      1. 13.4.1Book 0 / Page 2 / Register 0: Page Select Register - 0x00 / 0x02 / 0x00 (B0_P0_R0)
      2. 13.4.2Book 0 / Page 2 / Register 1-5: Reserved Register - 0x00 / 0x02 / 0x01-0x05 (B0_P1_R1-5)
      3. 13.4.3Book 0 / Page 2 / Register 6: Ramp Generator Frequency Register - 0x00 / 0x02 / 0x06 (B0_P2_R6)
      4. 13.4.4Book 0 / Page 2 / Register 7-23: Reserved Register - 0x00 / 0x02 / 0x07-0x17 (B0_P1_R7-23)
      5. 13.4.5Book 0 / Page 2 / Register 24: Inrush Optimization 1 Register - 0x00 / 0x02 / 0x18 (B0_P2_R24)
      6. 13.4.6Book 0 / Page 2 / Register 25: Inrush Optimization 2 Register - 0x00 / 0x02 / 0x19 (B0_P2_R25)
      7. 13.4.7Book 0 / Page 2 / Register 26: Inrush Optimization 3 Register - 0x00 / 0x02 / 0x1A (B0_P2_R25)
      8. 13.4.8Book 0 / Page 2 / Register 27: Inrush Optimization 4 Register - 0x00 / 0x02 / 0x1B (B0_P2_R25)
      9. 13.4.9Book 0 / Page 2 / Register 28-127: Reserved Register - 0x00 / 0x02 / 0x1C-0x7F (B0_P1_R28-127)
    5. 13.5 Book 100 Page 0
      1. 13.5.1 Book 100 / Page 0 / Register 0: Page Select Register - 0x64 / 0x00 / 0x00 (B100_P0_R0)
      2. 13.5.2 Book 100 / Page 0 / Register 1: DAC Interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
      3. 13.5.3 Book 100 / Page 0 / Register 2: ADC interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
      4. 13.5.4 Book 100 / Page 0 / Register 3-6: Reserved Register - 0x64 / 0x00 / 0x03-0x06 (B100_P0_R3-6)
      5. 13.5.5 Book 100 / Page 0 / Register 7: DSP Mute Register - 0x64 / 0x00 / 0x07 (B100_P0_R7)
      6. 13.5.6 Book 100 / Page 0 / Register 8-15: Reserved Register - 0x64 / 0x00 / 0x08-0x0F (B100_P0_R8-15)
      7. 13.5.7 Book 100 / Page 0 / Register 16: Interrupt 1 DSP Register - 0x64 / 0x00 / 0x10 (B100_P0_R16)
      8. 13.5.8 Book 100 / Page 0/ Register 17: Interrupt 2 DSP Register - 0x64 / 0x00 / 0x11 (B100_P0_R17)
      9. 13.5.9 Book 100 / Page 0 / Register 18: Condition 1 DSP Register - 0x64 / 0x00 / 0x12 (B100_P0_R18)
      10. 13.5.10Book 100/ Page 0 / Register 19: Condition 2 DSP Register - 0x64 / 0x00 / 0x13 (B100_P0_R19)
      11. 13.5.11Book 100 / Page 0 / Register 20: ISR and COND Control Register - 0x64 / 0x00 / 0x14 (B100_P0_R20)
      12. 13.5.12Book 100 / Page 0/ Register 21: DSP Control Register - 0x64 / 0x00 / 0x15 (B100_P0_R21)
      13. 13.5.13Book 100 / Page 0 / Register 22-26: Reserved Register - 0x64 / 0x00 / 0x16-0x1A (B100_P0_R22-26)
      14. 13.5.14Book 100 / Page 0 / Register 27:PLL CLKIN Divider Register - 0x64 / 0x00 / 0x1B (B100_P0_R27)
      15. 13.5.15Book 100 / Page 0 / Register 28:PLL J-VAL Divider Register - 0x64 / 0x00 / 0x1C (B100_P0_R28)
      16. 13.5.16Book 100 / Page 0 / Register 29:PLL D-VAL Divider 2 Register - 0x64 / 0x00 / 0x1D (B100_P0_R29)
      17. 13.5.17Book 100 / Page 0 / Register 30:PLL D-VAL Divider 1 Register - 0x64 / 0x00 / 0x1E (B100_P0_R30)
      18. 13.5.18Book 100 / Page 0 / Register 31:DSP Clock Register - 0x64 / 0x00 / 0x1F (B100_P0_R31)
      19. 13.5.19Book 100 / Page 0 / Register 32: N-VAL Divider Register - 0x64 / 0x00 / 0x20 (B100_P0_R32)
      20. 13.5.20Book 100 / Page 0 / Register 33: MDAC-VAL Divider Register - 0x64 / 0x00 / 0x21 (B100_P0_R33)
      21. 13.5.21Book 100 / Page 0 / Register 34: MADC-VAL Divider Register - 0x64 / 0x00 / 0x22 (B100_P0_R34)
      22. 13.5.22Book 100 / Page 0 / Register 35-37: Reserved Register - 0x64 / 0x00 / 0x23-0x25 (B100_P0_R35-37)
      23. 13.5.23Book 100 / Page 0 / Register 38: Charge-pump Clock Register - 0x64 / 0x00 / 0x26 (B100_P0_R38)
      24. 13.5.24Book 100 / Page 0 / Register 39: Boost Clock Register - 0x64 / 0x00 / 0x27 (B100_P0_R39)
      25. 13.5.25Book 100 / Page 0 / Register 40: Ramp Clock 1 Register - 0x64 / 0x00 / 0x28 (B100_P0_R40)
      26. 13.5.26Book 100 / Page 0 / Register 41-42: Reserved Register - 0x64 / 0x00 / 0x29-0x2A (B100_P0_R41-42)
      27. 13.5.27Book 100 / Page 0 / Register 43: Ramp Clock 2 Register - 0x64 / 0x00 / 0x2B (B100_P0_R43)
      28. 13.5.28Book 100 / Page 0 / Register 44: Ramp Clock 3 Register - 0x64 / 0x00 / 0x2C (B100_P0_R44)
      29. 13.5.29Book 100 / Page 0/ Register 45-126: Reserved Register - 0x64 / 0x01 / 0x2D-0x7E (B100_P0_R45-126)
      30. 13.5.30Book 100 / Page 0 / Register 127: Book Selection Register - 0x64 / 0x00 / 0x7F (B100_P0_R127)
  14. 14器件和文档支持
    1. 14.1文档支持
    2. 14.2社区资源
    3. 14.3商标
    4. 14.4静电放电警告
    5. 14.5Glossary
  15. 15机械、封装和可订购信息
    1. 15.1封装尺寸

Register Map

See the General I2C Operation section for more details on addressing. Register settings should be set based on the files generated from the PPC3 GUI. Because the TAS2555 device is a complex system including the internal software, changes made in the TAS2555 registers not known in the PPC3 generated configurations can result in the speaker protection not operating correctly. Changes should be made from within PurePath Console 3 Software TAS2555 Application instead of manually changing registers when possible. New configuration files can be generated from PPC3 to prevent invalid configurations.

Register Map Summary

Table 6. Summary of Register Map

DecimalHexDESCRIPTION
BOOK NO.PAGE NO.REG. NO.BOOK NO.PAGE NO.REG. NO.
0000x000x000x00Page Select
0010x000x000x01Software Reset
002-30x000x000x02-0x03Reserved
0040x000x000x04Power Control
0050x000x000x05Power Control 2
0060x000x000x06Speaker Control
0070x000x000x07Mute
0080x000x000x08Channel Control
009-310x000x000x09-0x1FReserved
00320x000x000x20CRC Checksum
00330x000x000x21Checksum Reset
00340x000x000x22Device DSP Mode
0035-390x000x000x23-0x27Reserved
00400x000x000x28Class-D SSM Mode
00410x000x000x29Reserved
00420x000x000x2ADigital Playback Control
00430x000x000x2BCurrent Limit
00440x000x000x2CClock Error Control 1
00450x000x000x2DClock Error Control 2
00460x000x000x2EClock Error Control 3
0047-990x000x000x2F-0x63Reserved
001000x000x000x64Power Up Flag
00101-1030x000x000x65-0x67Reserved
001040x000x000x68Interrupt Flags DAC & OCP/OTP Sticky
00105-1070x000x000x69-0x6BReserved
001080x000x000x6CDSP Interrupt Output Sticky
00109-1200x000x000x6D-0x78Reserved
001210x000x000x79Power Modes
00122-1260x000x000x7A-0x7EReserved
001270x000x000x7FBook Selection
0100x000x010x00Page Select
0110x000x010x01ASI1 DAC Format
0120x000x010x02ASI1 ADC Format
0130x000x010x03ASI1 Offset
014-60x000x010x04-0x06Reserved
0170x000x010x07ASI1 ADC Path
0180x000x010x08ASI1 DAC BCLK
0190x000x010x09ASI1 DAC WCLK
01100x000x010x0AASI1 ADC BCLK
01110x000x010x0BASI1 ADC WCLK
01120x000x010x0CASI1 DIN/DOUT MUX
01130x000x010x0DASI1 BDIV Clock Select
01140x000x010x0EASI1 BDIV Clock Ratio
01150x000x010x0FASI1 WDIV Clock Ratio
01160x000x010x10ASI1 DAC Clock Output
01170x000x010x11ASI1 ADC Clock Output
0118-200x000x010x12-0x14Reserved
01210x000x010x15ASI2 DAC Format
01220x000x010x16ASI2 ADC Format
01230x000x010x17ASI2 Offset
0124-260x000x010x18-0x1AReserved
01270x000x010x1BASI2 ADC Path
01280x000x010x1CASI2 DAC BCLK
01290x000x010x1DASI2 DAC WCLK
01300x000x010x1EASI2 ADC BCLK
01310x000x010x1FASI2 ADC WCLK
01320x000x010x20ASI2 DIN/DOUT MUX
01330x000x010x21ASI2 BDIV Clock Select
01340x000x010x22ASI2 BDIV Clock Ratio
01350x000x010x23ASI2 WDIV Clock Ratio
01360x000x010x24ASI2 DAC Clock Output
01370x000x010x25ASI2 ADC Clock Output
0138-600x000x010x26-0x3CReserved
01610x000x010x3DBCLK1_GPIO1 Pin
01620x000x010x3EWCLK1_GPIO2 Pin
01630x000x010x3FDOUT1_GPIO3 Pin
01640x000x010x40IRQ_GPIO4 Pin
01650x000x010x41BCLK2_GPIO5 Pin
01660x000x010x42WCLK2_GPIO6 Pinb
01670x000x010x43DOUT2_GPIO7 Pin
01680x000x010x44DIN2_GPIO8 Pin
01690x000x010x45ICC_CLK_GPIO9 Pin
01700x000x010x46ICC_GPIO10 Pin
0171-760x000x010x47-0x4CReserved
01770x000x010x4DGPI Pin
01780x000x010x4EReserved
01790x000x010x4FGPIO HIZ CTRL1
01800x000x010x50GPIO HIZ CTRL2
01810x000x010x51GPIO HIZ CTRL3
01820x000x010x52GPIO HIZ CTRL4
01830x000x010x53GPIO HIZ CTRL3
0184-860x000x010x54-0x56Reserved
01870x000x010x57GPIO Pin 1
01880x000x010x58GPIO Pin 2
01890x000x010x59GPIO Pin 3
0190-1070x000x010x5A-0x6BReserved
011080x000x010x6CInterrupt Control 1
011090x000x010x6DInterrupt Control 2
011100x000x010x6EInterrupt Control 3
011110x000x010x6FInterrupt Control 4
011120x000x010x70Interrupt Control 5
011130x000x010x71Interrupt Control 6
01114-1270x000x010x72-0xFFReserved Registers
0200x000x010x00Page Select Register
021-50x000x010x01-0x05Reserved Registers
0260x000x010x06Ramp Generator Frequency
027-230x000x010x07x17Reserved Registers
02240x000x010x18Inrush Optimization 1
02250x000x010x19Inrush Optimization 2
02260x000x010x1AInrush Optimization 3
02270x000x010x1BInrush Optimization 4
0228-1270x000x010x1C-0x7FReserved Registers
100000x640x000x00Page Select Register
100010x640x000x01DAC Interpolation
100020x640x000x02ADC interpolation Register
10003-60x640x000x03-0x06Reserved Registers
100070x640x000x07DSP Mute Register
10008-150x640x000x0FReserved Registers
1000160x640x000x10Interrupt 1 DSP
1000170x640x000x11Interrupt 2 DSP
1000180x640x000x12Condition 1 DSP
1000190x640x000x13Condition 2 DSP
1000200x640x000x14ISR and COND Control
1000210x640x000x15DSP Control Register
1000 22-260x640x000x16-0x1AReserved Register
1000270x640x000x1BPLL CLKIN Divider
1000280x640x000x1CPLL J-VAL Divider
1000290x640x000x1DPLL D-VAL Divider 2
1000300x640x000x1ED-VAL Divider 1
1000310x640x000x1FDSP Clock
1000320x640x000x20N-VAL Divider
1000330x640x000x21MDAC-VAL Divider
1000340x640x000x22MADC-VAL Divider
100035-370x640x000x23-0x25Reserved Register
1000380x640x000x26Charge-pump Clock
1000390x640x000x27Boost Clock
1000400x640x000x28Ramp Clock 1
100041-420x640x000x29-0x2AReserved Register
1000430x640x000x2BRamp Clock 2
1000440x640x000x2CRamp Clock 3
100045-1260x640x000x2D-0x7EReserved Register
10001270x640x000x7FBook Selection

Book 0 Page 0

Book 0 / Page 0 / Register 0: Page Select Register - 0x00 / 0x00 / 0x00 (B0_P0_R0)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0PAGER/W0000 0000Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table for details.

Book 0 / Page 0 / Register 1: Software Reset Register - 0x00 / 0x00 / 0x01 (B0_P0_R1)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D1RESERVEDR/W0000 000Reserved. Write only reset values.
D0RESETR/W0Self-clearing software reset bit. Set to value of 1 to reset.
0: Don't care
1: Self clearing software reset

Book 0 / Page 0 / Register 2-3: Reserved Registers - 0x00 / 0x00 / 0x02-0x03 (B0_P0_R2-3)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved.

Book 0 / Page 0 / Register 4: Power Control Register - 0x00 / 0x00 / 0x04 (B0_P0_R4)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7PCR_DSPR/W0 DSP is
0: powered-down
1: powered-up
D6PCR_PLLR/W00: PLL is
0: powered-down
1: powered-up
D5PCR_NR/W00: N divider is
0: powered-down
1: powered-up
D4PCR_MDACR/W00: MDAC divider is
0: powered-down
1: powered-up
D3PCR_MADCR/W00: MADC divider is
0: powered-down
1: powered-up
D2-D1RESERVEDR/W0Reserved. Write only reset values.
D0PCR_SDR/W00: Device software shutdown is
0: powered-down
1: powered-up (all blocks shut-down and goes into low power mode)

Book 0 / Page 0 / Register 5: Power Control Register 2 - 0x00 / 0x00 / 0x05 (B0_P0_R5)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7PCR_CLASSDR/W0 Class-D outputs are
0: Disabled
1: Enabled
D6RESERVEDR/W0Reserved. Write only reset values.
D5PCR_BOOSTR/W00: Boost is
0: Disabled
1: Enabled
D4-D2RESERVEDR/W000Reserved. Write only reset values.
D1PCR_ISNSR/W00: I-sense ADC is
0: Disabled
1: Enabled
D0PCR_VSNSR/W00: V-sense ADC is
0: Disabled
1: Enabled

Book 0 / Page 0 / Register 6: Speaker Control Register - 0x00 / 0x00 / 0x06 (B0_P0_R6)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D3DAC_GAINR/W1111DAC Playback channel gain (outside DSP) is
0000: 0dB
0001: 1dB
0010: 2dB
...
1110: 14dB
1111: 15dB
D2-D0DAC_EDGER/W100Class-D output edge rate control is
000: Reserved
001: Reserved
010: 29ns
011: 25ns
100: 14ns
101: 13ns
110: 12ns
111: 11ns

Book 0 / Page 0 / Register 7: Mute Register - 0x00 / 0x00 / 0x07 (B0_P0_R7)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5RESERVEDR/W000Reserved. Write only reset values.
D4-D2RESERVEDR/W000Reserved. Write only reset values.
D1MUTE_ISNSR/W10: Un-mute I-sense
1: Mute I-sense
D0MUTE_SPKR/W10: Un-mute Class-D
1: Mute Class-D

Book 0 / Page 0 / Register 8: Channel Control Register - 0x00 / 0x00 / 0x08 (B0_P0_R8)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D3RESERVEDR/W00000Reserved. Write only reset values.
D2-D1SENSE_GAINR/W00IVsense gain setting is
00: Isense channel full-scale output corresponds to 1.25A and Vsense channel full-scale output corresponds to 8.5V (recommended to use for 8-ohm )
01: Isense channel full-scale output corresponds to 1.48A and Vsense channel full-scale output corresponds to 8.5V (recommended to use for 6-ohm load case)
10: Isense channel full-scale output corresponds to 1.76A and Vsense channel full-scale output corresponds to 8.5V (recommended to use for 4-ohm load case)
11: Reserved
D0 VSENSE_ADCMR/W0 Vsense ADC is used for
0: sensing Class-D output voltage
1: analog input

Book 0 / Page 0 / Register 9-31: Reserved Registers - 0x00 / 0x00 / 0x09-0x1F (B0_P0_R9-31)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 0 / Register 32: CRC Checksum Register - 0x00 / 0x00 / 0x20 (B0_P0_R32)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0CRC_CHECKSUMRxxxx xxxxCRC checksum of all encrypted PRAM content downloaded to device since checksum reset

Book 0 / Page 0 / Register 33: Checksum Reset Register - 0x00 / 0x00 / 0x21 (B0_P0_R33)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D1RESERVEDR/W000 0000Reserved. Write only reset values.
D0CRC_RESETR/W0PRAM Checksum
0: PRAM download check-sum is not reset.
1: PRAM download check-sum is reset. (This is recommended to be done before PRAM code download so that after download the above checksum value can be read to confirm download process has any error )

Book 0 / Page 0 / Register 34: Device DSP Mode Register - 0x00 / 0x00 / 0x22 (B0_P0_R34)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6RESERVEDR/W00Reserved. Write only reset values.
D5MODE_COEFFR/W1Default coefficients are
0: from host. Host needs to download coefficients into device.
1: from internal ROM. Default coefficients for ROM modes.
D4-D2RESERVEDR/W000Reserved. Write only reset values.
D1-D0MODE_DSPR/W01DSP Mode is
00: SmartAmp Mode
01: ROM Mode 1: Digital input playback only
10: ROM Mode 2: Digital input with I/V-sense
11: Reserved

Book 0 / Page 0 / Register 35-39: Reserved Registers - 0x00 / 0x00 / 0x23-0x27 (B0_P0_R35-R39)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 0 / Register 40: Class-D SSM Mode Register - 0x00 / 0x00 / 0x28 (B0_P0_R40)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D1RESERVEDR/W000 0000Reserved. Write only default values.
D0RAMP_SSM_MODER/W0Ramp generator Spread Spectrum Mode (SSM) mode of operation is
0: Disabled.
1: Enabled. This is supported only when Class-D RAMP_CLK is generated using on-chip RAMP CLK generator, which can be configured using B100_P0_R40.

Book 0 / Page 0 / Register 41: Reserved Registers - 0x00 / 0x00 / 0x29 (B0_P0_R41)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 0 / Register 42: Digital Playback Control Register - 0x00 / 0x00 / 0x2A (B0_P0_R42)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5RESERVEDR/W000Reserved. Write only reset values.
D4-D3ASI2_CHANNELR/W0ASI2 Playback Input
00: ASI2 Left channel is used
01: ASI2 Right channel is used
10: ASI2 (Left+Right)/2 is used
11: ASI2 monoPCM input expected
D2-D1ASI1_CHANNELR/W0ASI1 Playback Input
00: ASI1 Left channel is used
01: ASI1 Right channel is used
10: ASI1 (Left+Right)/2 is used
11: ASI1 monoPCM input expected
D0SOFT_MUTER/W0Soft Stepping of Mute/Un-Mute is
0: Enabled
1: Disabled

Book 0 / Page 0 / Register 43: Current Limit Register - 0x00 / 0x00 / 0x2B (B0_P0_R43)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D2RESERVEDR/W0000 00Reserved. Write only reset values.
D1-D0BOOST_ILIMITR/W11Boost current limit is
00: 1.5A
01: 2.0A
10: 2.5A
11: 3.0A

Book 0 / Page 0 / Register 44: Clock Error Control 1 Register - 0x00 / 0x00 / 0x2C (B0_P0_R44)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5RESERVEDR000Reserved. Write only reset values.
D4CLK_ERR1_INPUTR/W0Clock error detection 1 input clock is
0: ASI1
1: ASI2
D3-D2CLK_ERR2_INPUTR/W00Clock error detection 2 input clock is
00: DAC modulator clock
01: ADC modulator clock
10: PLL clock
11: Reserved
D1CLK_ERR1_ENR/W0Clock error detection 1 is
0: Disable
1: Enable
D0CLK_ERR2_ENR/W0Clock error detection 2 is
0: Disable
1: Enable

Book 0 / Page 0 / Register 45: Clock Error Control 2 Register - 0x00 / 0x00 / 0x2D (B0_P0_R45)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D3RESERVEDR0001 0Reserved. Write only reset values.
D2-D0CLK_ERR1_TOR/W111Clock error detection 1 shutdown timeout. B0_P0_R4[0] will be 1 after shutdown. Program that bit to 0 before powering up the device again. Chip will shutdown if a valid clock is not applied to error detection1 block for
000: 11ms
001: 22ms
010: 44ms
011: 87ms
100: 174ms
101: 350ms
110: 700ms
111: 1.4s

Book 0 / Page 0 / Register 46: Clock Error Control 3 Register - 0x00 / 0x00 / 0x2E (B0_P0_R46)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D3RESERVEDR0001 0Reserved. Write only reset values.
D2-D0CLK_ERR2_TOR/W111Clock error detection 2 shutdown timeout. B0_P0_R4[0] will be 1 after shutdown. Program that bit to 0 before powering up the device again. Chip will shutdown if a valid clock is not applied to error detection2 block for
000: 11ms
001: 22ms
010: 44ms
011: 87ms
100: 174ms
101: 350ms
110: 700ms
111: 1.4s

Book 0 / Page 0 / Register 47-99: Reserved Registers - 0x00 / 0x00 / 0x2F-0x63 (B0_P0_R47-R99)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 0 / Register 100: Power Up Flag Register - 0x00 / 0x00 / 0x64 (B0_P0_R100)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7PWR_DACR0DAC Power is
0: DAC Powered Down
1: DAC Powered Up
D6PWR_SPKR0Class D Power is
0: Class D Powered Down
1: Class D Powered Up
D5PWR_BOOSTR0Boost Power is
0: Boost Powered Down
1: Boost Powered Up
D4BOOST_PT_ENR0Boost Pass-through is
0: Boost Pass-through disable
1: Boost Pass-through enable
D3PWR_ISENSER0ISense ADC Power is
0: ISense ADC Powered Down
1: ISense ADC Powered Up
D2PWR_VSENSER0VSense ADC Power is
0: VSense ADC Powered Down
1: VSense ADC Powered Up
D1-D0RESERVEDR00Reserved

Book 0 / Page 0 / Register 101-103: Reserved Registers - 0x00 / 0x00 / 0x65-0x67 (B0_P0_R101-R103)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 0 / Register 104: Interrupt Flags DAC & OCP/OTP Sticky Register - 0x00 / 0x00 / 0x68 (B0_P0_R104)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7OVER_CURRENTR0SPK Over-current STICKY - Cleared once read is
0: SPK Over-current is not detected
1: SPK Over-current is detected
D6UNDER_VOLTAGER0SPK Over-voltage STICKY - Cleared once read is
0: Analog supplies under voltage is not detected
1: Analog supplies under voltage is detected
D5RESERVEDR0Reserved
D4OVER_TEMPR0Over-temperature STICKY - Cleared once read is
0: Over-temperature is not detected
1: Over-temperature is detected
D3BROWNOUTR0Brownout STICKY - Cleared once read is
0: Normal supply is present
1: Brownout condition is detected
D2CLK_PRESENTR0Clock Present STICKY - Cleared once read is
0: Clock is present
1: Clock is lost
D1SAR_COMPLETER0SAR complete STICKY - Cleared once read is
0: SAR has not completed
1: SAR complete
D0RESERVEDR0Reserved

Book 0 / Page 0 / Register 105-107: Reserved Registers - 0x00 / 0x00 / 0x69-0x6B (B0_P0_R105-R107)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 0 / Register 108: DSP Interrupt Output Sticky Register - 0x00 / 0x00 / 0x6C (B0_P0_R108)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7INT1R0DSP output Interrupt1 Port Output STICKY - Cleared once read
D6INT2R0DSP output Interrupt2 Port Output STICKY - Cleared once read
D5INT3R0DSP output Interrupt3 Port Output STICKY - Cleared once read
D4INT4R0DSP output Interrupt4 Port Output STICKY - Cleared once read
D3-D0RESERVEDR0000Reserved

Book 0 / Page 0 / Register 109-120: Reserved Registers - 0x00 / 0x00 / 0x6D-0x78 (B0_P0_R109-R120)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 0 / Register 121: Power Modes Register - 0x00 / 0x00 / 0x79 (B0_P0_R121)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7LOW_POWER_ENR/W0 Low-power sleep mode is
0: Disabled
1: Enabled - Set high only when AVDD and VBAT supplies are available in the system.
D6-D0RESERVEDR/W000 0000Reserved. Write only reset values.

Book 0 / Page 0 / Register 122-126: Reserved Registers - 0x00 / 0x00 / 0x7A-0x7E (B0_P0_R122-R126)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 0 / Register 127: Book Selection Register - 0x00 / 0x00 / 0x7F (B0_P0_R127)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0BOOKR/W0000 00000-255: Selects the Register Book for next read or write command.

Book 0 Page 1

Book 0 / Page 1 / Register 0: Page Select Register - 0x00 / 0x01 / 0x00 (B0_P1_R0)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0PAGER/W0000 0001Page Select Register is
0-255: Selects the Register Page for next read or write command.
Refer Table for details.

Book 0 / Page 1 / Register 1: ASI1 DAC Format Register - 0x00 / 0x01 / 0x01 (B0_P1_R1)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5ASI1D_INTERFACER/W000ASI1 DAC interface is
000: I2S
001: DSP
010: Right-Justified (RJF). Non-zero values of ASI1_OFFSET1 not supported.
011: Left-Justified (LJF)
100: MonoPCM
101-111: Reserved
D4-D3ASI1D_WORD_LEN R/W10ASI1 DAC word length is
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
D2-D1RESERVEDR/W00Reserved. Write only reset values.
D0ASI1_TRISTATER/W0Tri-stating of DOUT1 for the extra ASI1_BCLK cycles after Data Transfer is over for a frame is
0: Disabled
1: Enabled

Book 0 / Page 1 / Register 2: ASI1 ADC Format Register - 0x00 / 0x01 / 0x02 (B0_P1_R2)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5ASI1A_INTERFACER/W000ASI1 ADC Interface (This register control is valid only if D0 = 1)
000: I2S
001: DSP
010: RJF. non-zero values of ASI1_OFFSET1 not supported.
011: LJF
100: MonoPCM
101-111: Reserved
D4-D3ASI1A_WORD_LEN R/W00ASI1 ADC word length (This register control is valid only if D0 = 1)
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
D2-D1RESERVEDR/W00Reserved. Write only reset values.
D0ASI1A_USE_DACR/W0ASI1 ADC uses
0: the same Interface type and word length as DAC side as in B0_P1_R1
1: the Interface type and word length from B0_P1_R2[7:3]

Book 0 / Page 1 / Register 3: ASI1 Offset Register - 0x00 / 0x00 / 0x03 (B0_P1_R3)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0ASI1_OFFSETR/W0000 0000ASI1_OFFSET = x ASI1_BCLK's. Offset is measured with respect to WCLK-rising edge in DSP Mode. Offset is not supported for RJF mode
0000 0000: 0 ASI1_BCLK's
0000 0001: 1 ASI1_BCLK's
...
1111 1110: 254 ASI1_BCLK's
1111 1111: 255 ASI1_BCLK's

Book 0 / Page 1 / Register 4-6: Reserved Registers - 0x00 / 0x01 / 0x04-0x06 (B0_P1_R4-6)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved.

Book 0 / Page 1 / Register 7: ASI1 ADC Path Register - 0x00 / 0x01 / 0x07 (B0_P1_R7)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D3RESERVEDR/W0000 0Reserved. Write only reset values.
D2-D0ASI1A_PATHR/W001ASI1 ADC path is
000: ASI1_ADC_DATA is disabled. No serial data output from ASI1
001: ASI1_ADC_DATA <Left,Right> = DSP_OUT<Left,Right>
010: Reserved
011: Reserved
100: Reserved
101: ASI1_ADC_DATA<Left,Right> = ASI1_CHANNEL<Left,Right>
110: ASI1_ADC_DATA<L1,R1> = ASI2_CHANNEL<Left,Right>
111: Reserved

Book 0 / Page 1 / Register 8: ASI1 DAC BCLK Register - 0x00 / 0x01 / 0x08 (B0_P1_R8)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D3ASI1D_BCLK_PATHR/W0000ASI1_DAC_BCLK input from
0000: GPIO1 (Preferred pin usage)
0001: GPIO2
0010: GPIO3
0011: GPIO4
0100: GPIO5
0101: GPIO6
0110: GPIO7
0111: GPIO8
1000: GPIO9
1001: GPIO10
1010: Reserved
1011: Reserved
1100: GPI1
1101: GPI2
1110: GPI3
1111: Reserved
D2RESERVEDR/W0Reserved. Write only reset values.
D1ASI1D_BCLK_EDGER/W0ASI1_DAC_BCLK timing per protocol is
0: normal
1: inverted
D0AS1_BWCLK_MODER/W0ASI1 BCLK /WCLK output mode
0: ASI1_DAC_BCLK and ASI1_DAC_WCLK are active in output modes only when ASI1 is active and/or codec is powered up
1: ASI1_DAC_BCLK and ASI1_DAC_WCLK are free running.

Book 0 / Page 1 / Register 9: ASI1 DAC WCLK Register - 0x00 / 0x01 / 0x09 (B0_P1_R9)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D3ASI1D_WCLK_PATHR/W0001ASI1_DAC_WCLK input from
0000: GPIO1
0001: GPIO2 (Preferred pin usage)
0010: GPIO3
0011: GPIO4
0100: GPIO5
0101: GPIO6
0110: GPIO7
0111: GPIO8
1000: GPIO9
1001: GPIO10
1010: Reserved
1011: Reserved
1100: GPI1
1101: GPI2
1110: GPI3
1111: Reserved
D2RESERVEDR/W0 Reserved. Write only reset values.
D1ASI1D_WCLK_EDGER/W0ASI1_DAC_WCLK timing per protocol
0: normal
1: inverted
D0RESERVEDR/W0Reserved. Write only reset values.

Book 0 / Page 1 / Register 10: ASI1 ADC BCLK Register - 0x00 / 0x01 / 0x0A (B0_P1_R10)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D3ASI1A_BCLK_PATHR/W1111ASI1_ADC_BCLK input from
0000: GPIO1
0001: GPIO2
0010: GPIO3
0011: GPIO4
0100: GPIO5
0101: GPIO6
0110: GPIO7
0111: GPIO8
1000: GPIO9
1001: GPIO10
1010: Reserved
1011: Reserved
1100: GPI1
1101: GPI2
1110: GPI3
1111: ASI1_DAC_BCLK_PATH B0_P1_R8[6:3] (Preferred usage)
D2RESERVEDR/W0Reserved. Write only reset values.
D1ASI1A_BCLK_EDGER/W0ASI1_ADC_BCLK timing per protocol is
0: normal
1: inverted
D0RESERVEDR/W0Reserved. Write only reset values.

Book 0 / Page 1 / Register 11: ASI1 ADC WCLK Register - 0x00 / 0x01 / 0x0B (B0_P1_R11)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D3ASI1A_WCLK_PATHR/W1111ASI1_ADC_WCLK input from
0000: GPIO1
0001: GPIO2
0010: GPIO3
0011: GPIO4
0100: GPIO5
0101: GPIO6
0110: GPIO7
0111: GPIO8
1000: GPIO9
1001: GPIO10
1010: Reserved
1011: Reserved
1100: GPI1
1101: GPI2
1110: GPI3
1111: ASI1_ADC_WCLK_PATH B0_P1_R9[6:3] (Preferred usage)
D2RESERVEDR/W0Reserved. Write only reset values.
D1ASI1A_WCLK_EDGER/W0ASI1_ADC_WCLK timing per protocol is
0: normal
1: inverted
D0RESERVEDR/W0Reserved. Write only reset values.

Book 0 / Page 1 / Register 12: ASI1 DIN/DOUT MUX Register - 0x00 / 0x01 / 0x0C (B0_P1_R12)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D3ASI1_DIN_PATHR/W1100ASI1_DIN input from
0000: GPIO1
0001: GPIO2
0010: GPIO3
0011: GPIO4
0100: GPIO5
0101: GPIO6
0110: GPIO7
0111: GPIO8
1000: GPIO9
1001: GPIO10
1010: Reserved
1011: Reserved
1100: GPI1 (Preferred pin usage)
1101: GPI2
1110: GPI3
1111: Reserved
D2RESERVEDR/W0Reserved. Write only reset values.
D1-D0ASI1_DOUT_PATHR/W00ASI1_DOUT output from
00: Direct DOUT path (pin to pin loopback disabled)
01: ASI1_DIN ( Pin to Pin Loopback )
10: ASI2_DIN ( Pin to Pin Loopback )
11: Reserved

Book 0 / Page 1 / Register 13: ASI1 BDIV Clock Select Register - 0x00 / 0x01 / 0x0D (B0_P1_R13)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D3RESERVEDR/W0000 0Reserved. Write only reset values.
D2-D0ASI1_BDIV_CLKINR/W001ASI1_BDIV_CLKIN is
000: NDIV_CLK (Generated On-Chip)
001: DAC_MOD_CLK (Generated On-Chip)
010: Reserved
011: ADC_MOD_CLK (Generated On-Chip)
100: ASI1_DAC_BCLK (at pin)
101: ASI1_ADC_BCLK (at pin)
110: ASI2_DAC_BCLK (at pin)
111: ASI2_ADC_BCLK (at pin)

Book 0 / Page 1 / Register 14: ASI1 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x0E (B0_P1_R14)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7ASI1_BDIV_PWRR/W0ASI1_BDIV divider is
0: powered down
1: powered up
D6-D0ASI1_BDIV_RATIOR/W000 0010ASI1_BDIV
000 0000: 128
000 0001: 1
000 0010: 2
...
111 1110: 126
111 1111: 127

Book 0 / Page 1 / Register 15: ASI1 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x0F (B0_P1_R15)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7ASI1_WDIV_PWRR/W0ASI1_WDIV divider is
0: powered down
1: powered up
D6-D0ASI1_WDIV_RATIOR/W010 0000ASI1_WDIV
000 0000: 128
000 0001: 1
...
010 0000 :32
...
111 1110: 126
111 1111: 127

Book 0 / Page 1 / Register 16: ASI1 DAC Clock Output Register - 0x00 / 0x01 / 0x10 (B0_P1_R16)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W 0Reserved. Write only reset values.
D6-D4ASI1D_BCLK_OUTR/W000ASI1_DAC_BCLK_OUT
000: ASI1_BDIV_OUT
001: ASI1_DAC_BCLK
010: ASI1_ADC_BCLK
011: ASI2_BDIV_OUT
100: ASI2_DAC_BCLK
101: ASI2_ADC_BCLK
110: Reserved
111: Reserved
D3RESERVEDR/W 0Reserved. Write only reset values.
D2-D0ASI1D_WCLK_OUT R/W001ASI1_DAC_WCLK_OUT
000: ASI1_WDIV_OUT
001: ASI1_DAC_WCLK
010: ASI1_ADC_WCLK
011: ASI2_WDIV_OUT
100: ASI2_DAC_WCLK
101: ASI2_ADC_WCLK
110: Reserved
111: Reserved

Book 0 / Page 1 / Register 17: ASI1 ADC Clock Output Register - 0x00 / 0x01 / 0x11 (B0_P1_R17)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W 0Reserved. Write only reset values.
D6-D4ASI1A_BCLK_OUTR/W000ASI1_ADC_BCLK_OUT
000: ASI1_BDIV_OUT
001: ASI1_DAC_BCLK
010: ASI1_ADC_BCLK
011: ASI2_BDIV_OUT
100: ASI2_DAC_BCLK
101: ASI2_ADC_BCLK
110: Reserved
111: Reserved
D3RESERVEDR/W 0Reserved. Write only reset values.
D2-D0ASI1A_WCLK_OUTR/W001ASI1_ADC_WCLK_OUT
000: ASI1_WDIV_OUT
001: ASI1_DAC_WCLK
010: ASI1_ADC_WCLK
011: ASI2_WDIV_OUT
100: ASI2_DAC_WCLK
101: ASI2_ADC_WCLK
110: Reserved
111: Reserved

Book 0 / Page 1 / Register 18-20: Reserved Registers - 0x00 / 0x01 / 0x12-0x14 (B0_P1_R18-20)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved.

Book 0 / Page 1 / Register 21: ASI2 DAC Format Register - 0x00 / 0x01 / 0x15 (B0_P1_R21)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5ASI2D_INTERFACER/W000ASI2 DAC interface is
000: I2S
001: DSP
010: Right Justified (RJF). Non-zero values of ASI2_OFFSET not supported.
011: Left Justified (LJF)
100: MonoPCM
101-111: Reserved
D4-D3ASI2D_WORD_LEN R/W10ASI2 DAC word length is
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
D2-D1RESERVEDR/W00Reserved. Write only reset values.
D0ASI2_TRISTATER/W0Tristating of DOUT1 for the extra ASI2_BCLK cycles after Data Transfer is over for a frame
0: Disabled
1: Enabled

Book 0 / Page 1 / Register 22: ASI2 ADC Format Register - 0x00 / 0x01 / 0x16 (B0_P1_R22)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5ASI2A_INTERFACER/W000ASI2 ADC interface is (This register control is valid only if D0 = 1)
000: I2S
001: DSP
010: Right Justified (RJF). Non-zero values of ASI2_OFFSET not supported.
011: Left Justified (LJF)
100: MonoPCM
101-111: Reserved
D4-D3ASI2A_WORD_LEN R/W00ASI2 ADC word length is (This register control is valid only if D0 = 1)
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
D2-D1RESERVEDR/W00Reserved. Write only reset values.
D0ASI2A_USE_DACR/W0ASI2 ADC uses
0: the same Interface type and word length as DAC side as in B0_P1_R1
1: the Interface type and word length from B0_P1_R2[7:3]

Book 0 / Page 1 / Register 23: ASI2 Offset Register - 0x00 / 0x01 / 0x17 (B0_P1_R23)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0ASI2_OFFSETR/W0000 0000ASI2_OFFSET = x ASI2_BCLK's. Offset is measured with respect to WCLK-rising edge in DSP Mode. Offset is not supported for RJF mode
0000 0000: 0 ASI2_BCLK's
0000 0001: 1 ASI2_BCLK's
...
1111 1110: 254 ASI2_BCLK's
1111 1111: 255 ASI2_BCLK's

Book 0 / Page 1 / Register 24-26: Reserved Registers - 0x00 / 0x01 / 0x18-0x1A (B0_P1_R24-26)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved.

Book 0 / Page 1 / Register 27: ASI2 ADC Path Register - 0x00 / 0x01 / 0x1B (B0_P1_R27)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D3RESERVEDR0000 0Reserved. Write only reset values.
D2-D0ASI2A_PATHR/W010ASI2 ADC Path is
000: ASI2_ADC_DATA is disabled. No serial data output from ASI2
001: Reserved
010: ASI2_ADC_DATA <Left,Right> = DSP_OUT<Left,Right>
011: Reserved
100: Reserved
101: ASI1_ADC_DATA<Left,Right> = ASI1_CHANNEL<Left,Right>
110: ASI1_ADC_DATA<Left,Right> = ASI2_CHANNEL<Left,Right>
111: Reserved

Book 0 / Page 1 / Register 28: ASI2 DAC BCLK Register - 0x00 / 0x01 / 0x1C (B0_P1_R28)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D3ASI2D_BCLK_PATHR/W0100ASI1_DAC_BCLK input from
0000: GPIO1
0001: GPIO2
0010: GPIO3
0011: GPIO4
0100: GPIO5 (Preferred pin usage)
0101: GPIO6
0110: GPIO7
0111: GPIO8
1000: GPIO9
1001: GPIO10
1010: Reserved
1011: Reserved
1100: GPI1
1101: GPI2
1110: GPI3
1111: Reserved
D2RESERVEDR/W0Reserved. Write only reset values.
D1ASI2D_BCLK_EDGER/W0ASI2_DAC_BCLK timing per protocol is
0: normal
1: inverted
D0ASI2_BWCLK_MODER/W0ASI2 BCLK /WCLK output mode is
0: ASI2_DAC_BCLK and ASI2_DAC_WCLK are active in output modes only when ASI2 is active and/or codec is powered up
1: ASI2_DAC_BCLK and ASI2_DAC_WCLK are free running.

Book 0 / Page 1 / Register 29: ASI2 DAC WCLK Register - 0x00 / 0x01 / 0x1D (B0_P1_R29)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D3ASI2_WCLK_PATHR/W0101ASI2_DAC_WCLK input from
0000: GPIO1
0001: GPIO2
0010: GPIO3
0011: GPIO4
0100: GPIO5
0101: GPIO6 (Preferred pin usage)
0110: GPIO7
0111: GPIO8
1000: GPIO9
1001: GPIO10
1010: Reserved
1011: Reserved
1100: GPI1
1101: GPI2
1110: GPI3
1111: Reserved
D2RESERVEDR/W0Reserved. Write only reset values.
D1ASI2D_WCLK_EDGER/W0ASI2_DAC_WCLK timing per protocol is
0: normal
1: inverted
D0RESERVEDR/W0Reserved. Write only reset values.

Book 0 / Page 1 / Register 30: ASI2 ADC BCLK Register - 0x00 / 0x01 / 0x1E (B0_P1_R30)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D3ASI2A_BCLK_PATHR/W1111ASI2_ADC_BCLK input from
0000: GPIO1
0001: GPIO2
0010: GPIO3
0011: GPIO4
0100: GPIO5
0101: GPIO6
0110: GPIO7
0111: GPIO8
1000: GPIO9
1001: GPIO10
1010: Reserved
1011: Reserved
1100: GPI1
1101: GPI2
1110: GPI3
1111: ASI2_DAC_BCLK_PATH B0_P1_R28[6:3] (Preferred usage)
D2RESERVEDR/W0Reserved. Write only reset values.
D1ASI2A_BCLK_EDGER/W0ASI2_ADC_BCLK timing per protocol is
0: normal
1: inverted
D0RESERVEDR/W0Reserved. Write only reset values.

Book 0 / Page 1 / Register 31: ASI2 ADC WCLK Register - 0x00 / 0x01 / 0x1F (B0_P1_R31)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D3ASI1A_WCLK_PATHR/W1111ASI1_ADC_WCLK input from
0000: GPIO1
0001: GPIO2
0010: GPIO3
0011: GPIO4
0100: GPIO5
0101: GPIO6
0110: GPIO7
0111: GPIO8
1000: GPIO9
1001: GPIO10
1010: Reserved
1011: Reserved
1100: GPI1
1101: GPI2
1110: GPI3
1111: ASI2_DAC_WCLK_PATH B0_P1_R29[6:3] (Preferred usage)
D2RESERVEDR/W0Reserved. Write only reset values.
D1ASI1A_WCLK_EDGER/W0ASI2_ADC_WCLK timing per protocol is
0: normal
1: inverted
D0RESERVEDR/W0Reserved. Write only reset values.

Book 0 / Page 1 / Register 32: ASI2 DIN/DOUT MUX - 0x00 / 0x01 / 0x20 (B0_P1_R32)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D3ASI2_IPATHR/W0111ASI2_DIN input from
0000: GPIO1
0001: GPIO2
0010: GPIO3
0011: GPIO4
0100: GPIO5
0101: GPIO6
0110: GPIO7
0111: GPIO8 (Preferred pin usage)
1000: GPIO9
1001: GPIO10
1010: Reserved
1011: Reserved
1100: GPI1
1101: GPI2
1110: GPI3
1111: Reserved
D2RESERVEDR/W0Reserved. Write only reset values.
D1-D0ASI2_OPATHR/W00ASI2_DOUT output from
00: Direct DOUT path (pin to pin loopback disabled)
01: ASI1_DIN ( Pin to Pin Loopback )
10: ASI2_DIN ( Pin to Pin Loopback )
11: Reserved

Book 0 / Page 1 / Register 33: ASI2 BDIV Clock Select Register - 0x00 / 0x01 / 0x21 (B0_P1_R33)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D3RESERVEDR/W0000 0Reserved. Write only reset values.
D2-D0ASI1_BDIV_CLKINR/W001ASI2_BDIV_CLKIN
000: NDIV_CLK (Generated On-Chip)
001: DAC_MOD_CLK (Generated On-Chip)
010: Reserved
011: ADC_MOD_CLK (Generated On-Chip)
100: ASI1_DAC_BCLK (at pin)
101: ASI1_ADC_BCLK (at pin)
110: ASI2_DAC_BCLK (at pin)
111: ASI2_ADC_BCLK (at pin)

Book 0 / Page 1 / Register 34: ASI2 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x22 (B0_P1_R34)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7ASI2_BDIV_PWRR/W0ASI2_BDIV divider is
0: powered down
1: powered up
D6-D0ASI2_BDIV_RTOR/W000 0010ASI2_BDIV
000 0000: 128
000 0001: 1
000 0010: 2
...
111 1110: 126
111 1111: 127

Book 0 / Page 1 / Register 35: ASI2 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x23 (B0_P1_R35)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7ASI2_WDIV_PWRR/W0ASI2_WDIV divider is
0: powered down
1: powered up
D6-D0ASI2_WDIV_RTOR/W010 0000ASI2_BDIV Ratio
000 0000: 128
000 0001: 1
...
010 0000 :32
...
111 1110: 126
111 1111: 127

Book 0 / Page 1 / Register 36: ASI2 DAC Clock Output Register - 0x00 / 0x01 / 0x24 (B0_P1_R36)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W 0Reserved. Write only reset values.
D6-D4ASI2D_BCLKOR/W011ASI2_DAC_BCLK_OUT
000: ASI1_BDIV_OUT
001: ASI1_DAC_BCLK
010: ASI1_ADC_BCLK
011: ASI2_BDIV_OUT
100: ASI2_DAC_BCLK
101: ASI2_ADC_BCLK
110: Reserved
111: Reserved
D3RESERVEDR/W0Reserved. Write only reset values.
D2-D0ASI2D_WCLKO R/W011ASI2_DAC_WCLK_OUT
000: ASI1_WDIV_OUT
001: ASI1_DAC_WCLK
010: ASI1_ADC_WCLK
011: ASI2_WDIV_OUT
100: ASI2_DAC_WCLK
101: ASI2_ADC_WCLK
110: Reserved
111: Reserved

Book 0 / Page 1 / Register 37: ASI2 ADC Clock Output Register - 0x00 / 0x01 / 0x25 (B0_P1_R37)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W 0Reserved. Write only reset values.
D6-D4ASI2A_BCLKOR/W011ASI2_ADC_BCLK_OUT
000: ASI1_BDIV_OUT
001: ASI1_DAC_BCLK
010: ASI1_ADC_BCLK
011: ASI2_BDIV_OUT
100: ASI2_DAC_BCLK
101: ASI2_ADC_BCLK
110: Reserved
111: Reserved
D3RESERVEDR/W 0Reserved. Write only reset values.
D2-D0ASI2A_WCLKOR/W011ASI2_ADC_WCLK_OUT
000: ASI1_WDIV_OUT
001: ASI1_DAC_WCLK
010: ASI1_ADC_WCLK
011: ASI2_WDIV_OUT
100: ASI2_DAC_WCLK
101: ASI2_ADC_WCLK
110: Reserved
111: Reserved

Book 0 / Page 1 / Register 38-60: Reserved Registers - 0x00 / 0x01 / 0x26-0x3C (B0_P1_R38-60)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved.

Book 0 / Page 1 / Register 61: BCLK1_GPIO1 Pin Register - 0x00 / 0x01 / 0x3D (B0_P1_R61)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6GPIO1_OVALR/W0GPIO1 general purpose output value is
0: Low(0)
1: High(1)
D5RESERVEDR/W0Reserved. Write only reset values.
D4-D0GPIO1_FUNCTR/W0 0001Pin BCLK1_GPIO1 function is
0 0000: Disabled (Input and Output buffers powered down)
0 0001: Input mode
0 0010: Reserved
0 0011: Output = General Purpose Output level set by bit D6
0 0100: Output = General Purpose Output level set by B0_P1_R88 & B0_P1_R87
0 0101: Output = Reserved
0 0110: Output = CLKOUT Output
0 0111: Output = INT1 Interrupt Output
0 1000: Output = INT2 Interrupt Output
0 1001: Output = INT3 Interrupt Output
0 1010: Output = INT4 Interrupt Output
0 1011: Reserved
0 1100: Output = ASI1 word clock output
0 1101: Output = ASI1 bit clock output
0 1110: Output = ASI1_WCLK_ADC_OUT
0 1111: Output = ASI1_BCLK_ADC_OUT
1 0000: Output = ASI1_DOUT
1 0001: Output = ASI2_WCLK_OUT
1 0010: Output = ASI2_BCLK_OUT
1 0011: Output = ASI2_WCLK_ADC_OUT
1 0100: Output = ASI2_BCLK_ADC_OUT
1 0101: Output = ASI2_DOUT
1 0110: Output = ASIM_WCLK_OUT
1 0111: Output = ASIM_BCLK_OUT
1 1000: Output = ASIM_DOUT
1 1001: Reserved
...
1 1111: Reserved

Book 0 / Page 1 / Register 62: WCLK1_GPIO2 Pin Register - 0x00 / 0x01 / 0x3E (B0_P1_R62)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6GPIO2_OVALR/W0GPIO2 general purpose output value is
0: Low(0)
1: High(1)
D5RESERVEDR/W0Reserved. Write only reset values.
D4-D0GPIO2_FUNCR/W0 0001Pin WCLK1_GPIO2 function is
0 0000: Disabled (Input and Output buffers powered down)
0 0001: Input mode
0 0010: Reserved
0 0011: Output = General Purpose Output level set by bit D6
0 0100: Output = General Purpose Output level set by B0_P1_R88 & B0_P1_R87
0 0101: Output = Reserved
0 0110: Output = CLKOUT Output
0 0111: Output = INT1 Interrupt Output
0 1000: Output = INT2 Interrupt Output
0 1001: Output = INT3 Interrupt Output
0 1010: Output = INT4 Interrupt Output
0 1011: Reserved
0 1100: Output = ASI1_WCLK_OUT
0 1101: Output = ASI1_BCLK_OUT
0 1110: Output = ASI1_WCLK_ADC_OUT
0 1111: Output = ASI1_BCLK_ADC_OUT
1 0000: Output = ASI1_DOUT
1 0001: Output = ASI2_WCLK_OUT
1 0010: Output = ASI2_BCLK_OUT
1 0011: Output = ASI2_WCLK_ADC_OUT
1 0100: Output = ASI2_BCLK_ADC_OUT
1 0101: Output = ASI2_DOUT
1 0110: Output = ASIM_WCLK_OUT
1 0111: Output = ASIM_BCLK_OUT
1 1000: Output = ASIM_DOUT
1 1001: Reserved
...
1 1111: Reserved

Book 0 / Page 1 / Register 63: DOUT1_GPIO3 Pin Register - 0x00 / 0x01 / 0x3F (B0_P1_R63)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6GPIO3_OVALR/W0GPIO3 general purpose output value is
0: Low(0)
1: High(1)
D5RESERVEDR/W0Reserved. Write only reset values.
D4-D0GPIO3_FUNCR/W1 0000Pin DOUT1_GPIO3 function is
0 0000: Disabled (Input and Output buffers powered down)
0 0001: Input mode
0 0010: Reserved
0 0011: Output = General Purpose Output level set by bit D6
0 0100: Output = General Purpose Output level set by B0_P1_R88 & B0_P1_R87
0 0101: Output = Reserved
0 0110: Output = CLKOUT Output
0 0111: Output = INT1 Interrupt Output
0 1000: Output = INT2 Interrupt Output
0 1001: Output = INT3 Interrupt Output
0 1010: Output = INT4 Interrupt Output
0 1011: Reserved
0 1100: Output = ASI1_WCLK_OUT
0 1101: Output = ASI1_BCLK_OUT
0 1110: Output = ASI1_WCLK_ADC_OUT
0 1111: Output = ASI1_BCLK_ADC_OUT
1 0000: Output = ASI1_DOUT
1 0001: Output = ASI2_WCLK_OUT
1 0010: Output = ASI2_BCLK_OUT
1 0011: Output = ASI2_WCLK_ADC_OUT
1 0100: Output = ASI2_BCLK_ADC_OUT
1 0101: Output = ASI2_DOUT
1 0110: Output = ASIM_WCLK_OUT
1 0111: Output = ASIM_BCLK_OUT
1 1000: Output = ASIM_DOUT
1 1001: Reserved
...
1 1111: Reserved

Book 0 / Page 1 / Register 64: IRQ_GPIO4 Pin Register - 0x00 / 0x01 / 0x40 (B0_P1_R64)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6GPIO4_OVALR/W0GPIO4 general purpose output value is
0: Low(0)
1: High(1)
D5RESERVEDR/W0Reserved. Write only reset values.
D4-D0GPIO4_FUNCR/W0 0111Pin IRQ_GPIO4 function is
0 0000: Disabled (Input and Output buffers powered down)
0 0001: Input mode
0 0010: Reserved
0 0011: Output = General Purpose Output level set by bit D6
0 0100: Output = General Purpose Output level set by B0_P1_R88 & B0_P1_R87
0 0101: Output = Reserved
0 0110: Output = CLKOUT Output
0 0111: Output = INT1 Interrupt Output
0 1000: Output = INT2 Interrupt Output
0 1001: Output = INT3 Interrupt Output
0 1010: Output = INT4 Interrupt Output
0 1011: Reserved
0 1100: Output = ASI1_WCLK_OUT
0 1101: Output = ASI1_BCLK_OUT
0 1110: Output = ASI1_WCLK_ADC_OUT
0 1111: Output = ASI1_BCLK_ADC_OUT
1 0000: Output = ASI1_DOUT
1 0001: Output = ASI2_WCLK_OUT
1 0010: Output = ASI2_BCLK_OUT
1 0011: Output = ASI2_WCLK_ADC_OUT
1 0100: Output = ASI2_BCLK_ADC_OUT
1 0101: Output = ASI2_DOUT
1 0110: Output = ASIM_WCLK_OUT
1 0111: Output = ASIM_BCLK_OUT
1 1000: Output = ASIM_DOUT
1 1001: Reserved
...
1 1111: Reserved

Book 0 / Page 1 / Register 65: BCLK2_GPIO5 Pin Register - 0x00 / 0x01 / 0x41 (B0_P1_R65)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6GPIO5_OVALR/W0GPIO5 general purpose output value is
0: Low(0)
1: High(1)
D5RESERVEDR/W0Reserved. Write only reset values.
D4-D0GPIO5_FUNCR/W0 0000Pin BCLK2_GPIO5 function is
0 0000: Disabled (Input and Output buffers powered down)
0 0001: Input mode
0 0010: Reserved
0 0011: Output = General Purpose Output level set by bit D6
0 0100: Output = General Purpose Output level set by B0_P1_R88 & B0_P1_R87
0 0101: Output = Reserved
0 0110: Output = CLKOUT Output
0 0111: Output = INT1 Interrupt Output
0 1000: Output = INT2 Interrupt Output
0 1001: Output = INT3 Interrupt Output
0 1010: Output = INT4 Interrupt Output
0 1011: Reserved
0 1100: Output = ASI1_WCLK_OUT
0 1101: Output = ASI1_BCLK_OUT
0 1110: Output = ASI1_WCLK_ADC_OUT
0 1111: Output = ASI1_BCLK_ADC_OUT
1 0000: Output = ASI1_DOUT
1 0001: Output = ASI2_WCLK_OUT
1 0010: Output = ASI2_BCLK_OUT
1 0011: Output = ASI2_WCLK_ADC_OUT
1 0100: Output = ASI2_BCLK_ADC_OUT
1 0101: Output = ASI2_DOUT
1 0110: Output = ASIM_WCLK_OUT
1 0111: Output = ASIM_BCLK_OUT
1 1000: Output = ASIM_DOUT
1 1001: Reserved
...
1 1111: Reserved

Book 0 / Page 1 / Register 66: WCLK2_GPIO6 Pin Register - 0x00 / 0x01 / 0x42 (B0_P1_R66)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6GPIO6_OVALR/W0GPIO6 general purpose output value is
0: Low(0)
1: High(1)
D5RESERVEDR/W0Reserved. Write only reset values.
D4-D0GPIO6_FUNCR/W0 0000Pin WCLK2_GPIO6 function is
0 0000: Disabled (Input and Output buffers powered down)
0 0001: Input mode
0 0010: Reserved
0 0011: Output = General Purpose Output level set by bit D6
0 0100: Output = General Purpose Output level set by B0_P1_R88 & B0_P1_R87
0 0101: Output = Reserved
0 0110: Output = CLKOUT Output
0 0111: Output = INT1 Interrupt Output
0 1000: Output = INT2 Interrupt Output
0 1001: Output = INT3 Interrupt Output
0 1010: Output = INT4 Interrupt Output
0 1011: Reserved
0 1100: Output = ASI1_WCLK_OUT
0 1101: Output = ASI1_BCLK_OUT
0 1110: Output = ASI1_WCLK_ADC_OUT
0 1111: Output = ASI1_BCLK_ADC_OUT
1 0000: Output = ASI1_DOUT
1 0001: Output = ASI2_WCLK_OUT
1 0010: Output = ASI2_BCLK_OUT
1 0011: Output = ASI2_WCLK_ADC_OUT
1 0100: Output = ASI2_BCLK_ADC_OUT
1 0101: Output = ASI2_DOUT
1 0110: Output = ASIM_WCLK_OUT
1 0111: Output = ASIM_BCLK_OUT
1 1000: Output = ASIM_DOUT
1 1001: Reserved
...
1 1111: Reserved

Book 0 / Page 1 / Register 67: DOUT2_GPIO7 Pin Register - 0x00 / 0x01 / 0x43 (B0_P1_R67)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6GPIO7_OVALR/W0GPIO7 general purpose output value is
0: Low(0)
1: High(1)
D5RESERVEDR/W0Reserved. Write only reset values.
D4-D0GPIO7_FUNCR/W0 0000Pin DOUT2_GPIO7 function is
0 0000: Disabled (Input and Output buffers powered down)
0 0001: Input mode
0 0010: Reserved
0 0011: Output = General Purpose Output level set by bit D6
0 0100: Output = General Purpose Output level set by B0_P1_R88 & B0_P1_R87
0 0101: Output = Reserved
0 0110: Output = CLKOUT Output
0 0111: Output = INT1 Interrupt Output
0 1000: Output = INT2 Interrupt Output
0 1001: Output = INT3 Interrupt Output
0 1010: Output = INT4 Interrupt Output
0 1011: Reserved
0 1100: Output = ASI1_WCLK_OUT
0 1101: Output = ASI1_BCLK_OUT
0 1110: Output = ASI1_WCLK_ADC_OUT
0 1111: Output = ASI1_BCLK_ADC_OUT
1 0000: Output = ASI1_DOUT
1 0001: Output = ASI2_WCLK_OUT
1 0010: Output = ASI2_BCLK_OUT
1 0011: Output = ASI2_WCLK_ADC_OUT
1 0100: Output = ASI2_BCLK_ADC_OUT
1 0101: Output = ASI2_DOUT
1 0110: Output = ASIM_WCLK_OUT
1 0111: Output = ASIM_BCLK_OUT
1 1000: Output = ASIM_DOUT
1 1001: Reserved
...
1 1111: Reserved

Book 0 / Page 1 / Register 68: DIN2_GPIO8 Pin Register - 0x00 / 0x01 / 0x44 (B0_P1_R68)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6GPIO8_OVALR/W0GPIO8 general purpose output value is
0: Low(0)
1: High(1)
D5RESERVEDR/W0Reserved. Write only reset values.
D4-D0GPIO8_FUNCR/W0 0000Pin DIN2_GPIO8 function is
0 0000: Disabled (Input and Output buffers powered down)
0 0001: Input mode
0 0010: Reserved
0 0011: Output = General Purpose Output level set by bit D6
0 0100: Output = General Purpose Output level set by B0_P1_R88 & B0_P1_R87
0 0101: Output = Reserved
0 0110: Output = CLKOUT Output
0 0111: Output = INT1 Interrupt Output
0 1000: Output = INT2 Interrupt Output
0 1001: Output = INT3 Interrupt Output
0 1010: Output = INT4 Interrupt Output
0 1011: Reserved
0 1100: Output = ASI1_WCLK_OUT
0 1101: Output = ASI1_BCLK_OUT
0 1110: Output = ASI1_WCLK_ADC_OUT
0 1111: Output = ASI1_BCLK_ADC_OUT
1 0000: Output = ASI1_DOUT
1 0001: Output = ASI2_WCLK_OUT
1 0010: Output = ASI2_BCLK_OUT
1 0011: Output = ASI2_WCLK_ADC_OUT
1 0100: Output = ASI2_BCLK_ADC_OUT
1 0101: Output = ASI2_DOUT
1 0110: Output = ASIM_WCLK_OUT
1 0111: Output = ASIM_BCLK_OUT
1 1000: Output = ASIM_DOUT
1 1001: Reserved
...
1 1111: Reserved

Book 0 / Page 1 / Register 69: ICC_GPIO9 Pin(ICC_CLK) Register - 0x00 / 0x01 / 0x45 (B0_P1_R69)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6GPIO9_OVALR/W0GPIO9 general purpose output value is
0: Low(0)
1: High(1)
D5RESERVEDR/W0Reserved. Write only reset values.
D4-D0GPIO9_FUNCR/W0 0000Pin ICC_GPIO9 function is
0 0000: Disabled (Input and Output buffers powered down)
0 0001: Input mode
0 0010: Reserved
0 0011: Output = General Purpose Output level set by bit D6
0 0100: Output = General Purpose Output level set by B0_P1_R88 & B0_P1_R87
0 0101: Output = Reserved
0 0110: Output = CLKOUT Output
0 0111: Output = INT1 Interrupt Output
0 1000: Output = INT2 Interrupt Output
0 1001: Output = INT3 Interrupt Output
0 1010: Output = INT4 Interrupt Output
0 1011: Reserved
0 1100: Output = ASI1_WCLK_OUT
0 1101: Output = ASI1_BCLK_OUT
0 1110: Output = ASI1_WCLK_ADC_OUT
0 1111: Output = ASI1_BCLK_ADC_OUT
1 0000: Output = ASI1_DOUT
1 0001: Output = ASI2_WCLK_OUT
1 0010: Output = ASI2_BCLK_OUT
1 0011: Output = ASI2_WCLK_ADC_OUT
1 0100: Output = ASI2_BCLK_ADC_OUT
1 0101: Output = ASI2_DOUT
1 0110: Output = ASIM_WCLK_OUT
1 0111: Output = ASIM_BCLK_OUT
1 1000: Output = ASIM_DOUT
1 1001: Reserved
...
1 1111: Reserved

Book 0 / Page 1 / Register 70: ICC_GPIO10 Pin Register - 0x00 / 0x01 / 0x46 (B0_P1_R70)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6GPIO10_OUT_VALR/W0GPIO10 General Purpose Output Value
0: Low(0)
1: High(1)
D5RESERVEDR/W0Reserved. Write only reset values.
D4-D0GPIO10_FUNCR/W0 0000GPIO10 Function
0 0000: Disabled (Input and Output buffers powered down)
0 0001: Input mode
0 0010: Reserved
0 0011: Output = General Purpose Output level set by bit D6
0 0100: Output = General Purpose Output level set by B0_P1_R88 & B0_P1_R87
0 0101: Output = Reserved
0 0110: Output = CLKOUT Output
0 0111: Output = INT1 Interrupt Output
0 1000: Output = INT2 Interrupt Output
0 1001: Output = INT3 Interrupt Output
0 1010: Output = INT4 Interrupt Output
0 1011: Reserved
0 1100: Output = ASI1_WCLK_OUT
0 1101: Output = ASI1_BCLK_OUT
0 1110: Output = ASI1_WCLK_ADC_OUT
0 1111: Output = ASI1_BCLK_ADC_OUT
1 0000: Output = ASI1_DOUT
1 0001: Output = ASI2_WCLK_OUT
1 0010: Output = ASI2_BCLK_OUT
1 0011: Output = ASI2_WCLK_ADC_OUT
1 0100: Output = ASI2_BCLK_ADC_OUT
1 0101: Output = ASI2_DOUT
1 0110: Output = ASIM_WCLK_OUT
1 0111: Output = ASIM_BCLK_OUT
1 1000: Output = ASIM_DOUT
1 1001: Reserved
...
1 1111: Reserved

Book 0 / Page 1 / Register 71-76: Reserved Registers - 0x00 / 0x01 / 0x47-0x4C (B0_P1_R71-76)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 1 / Register 77: GPI Pins Register - 0x00 / 0x01 / 0x4D (B0_P1_R77)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6RESERVEDR/W00Reserved. Write only reset values.
D5-D4GPI3_FUNCR/W00Pin ICC_GPI3 is
00: Disabled (Input powered down)
01: In Input mode
10: Reserved
11: Reserved
D3-D2GPI2_FUNCR/W01Pin MCLK_GPI2 is
00: Disabled (Input powered down)
01: Input mode
10: Reserved
11: Reserved
D1-D0GPI1_FUNCR/W01Pin BCLK1_GPI1
00: Disabled (Input powered down)
01: Input mode
10: Reserved
11: Reserved

Book 0 / Page 1 / Register 78: Reserved Register - 0x00 / 0x01 / 0x4E (B0_P1_R78)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 1 / Register 79: GPIO HIZ CTRL1 Register - 0x00 / 0x01 / 0x4F (B0_P1_R79)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5RESERVEDR/W000Reserved. Write only reset values.
D4GPIO2_HIZR/W0GPIO2 output
000: Drives both LO/HI
001: Drives both LO/HI with buskeeper(weak pull-up/down). For use with outputs that my be tri-stated such as TDM
D3-D1RESERVEDR/W000Reserved. Write only reset values.
D0GPIO1_HIZR/W0GPIO1 output
000: Drives both LO/HI
001: Drives both LO/HI with buskeeper(weak pull-up/down). For use with outputs that my be tri-stated such as TDM

Book 0 / Page 1 / Register 80: GPIO HIZ CTRL2 Register - 0x00 / 0x01 / 0x50 (B0_P1_R80)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5RESERVEDR/W000Reserved. Write only reset values.
D4GPIO4_HIZR/W0GPIO4 output
000: Drives both LO/HI.
001: Drives both LO/HI with buskeeper(weak pull-up/down). For use with outputs that my be tri-stated such as TDM
D3-D1RESERVEDR/W000Reserved. Write only reset values.
D0GPIO3_HIZR/W0GPIO3 utput
000: Drives both LO/HI
001: Drives both LO/HI with buskeeper(weak pull-up/down). For use with outputs that my be tri-stated such as TDM

Book 0 / Page 1 / Register 81: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x51 (B0_P1_R81)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5RESERVEDR/W000Reserved. Write only reset values.
D4GPIO6_HIZR/W0GPIO6 output
000: Drives both LO/HI
001: Drives both LO/HI with buskeeper(weak pull-up/down). For use with outputs that my be tri-stated such as TDM
D3-D1RESERVEDR/W000Reserved. Write only reset values.
D0GPIO5_HIZR/W0GPIO5 output
000: Drives both LO/HI
001: Drives both LO/HI with buskeeper(weak pull-up/down). For use with outputs that my be tri-stated such as TDM

Book 0 / Page 1 / Register 82: GPIO HIZ CTRL4 Register - 0x00 / 0x01 / 0x52 (B0_P1_R82)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5RESERVEDR/W000Reserved. Write only reset values.
D4GPIO8_HIZR/W0GPIO8 output
000: Drives both LO/HI
001: Drives both LO/HI with buskeeper(weak pull-up/down). For use with outputs that my be tri-stated such as TDM
D3-D1RESERVEDR/W000Reserved. Write only reset values.
D0GPIO7_HIZR/W0GPIO7 output
000: Drives both LO/HI
001: Drives both LO/HI with buskeeper(weak pull-up/down). For use with outputs that my be tri-stated such as TDM

Book 0 / Page 1 / Register 83: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x53 (B0_P1_R83)

BITREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5RESERVEDR/W000Reserved. Write only reset values.
D4GPIO10_HIZR/W0GPIO10 output
000: Drives both LO/HI
001: Drives both LO/HI with buskeeper(weak pull-up/down). For use with outputs that my be tri-stated such as TDM
D3-D1RESERVEDR/W000Reserved. Write only reset values.
D0GPIO9_HIZR/W0GPIO9 output
000: Drives both LO/HI
001: Drives both LO/HI with buskeeper(weak pull-up/down). For use with outputs that my be tri-stated such as TDM

Book 0 / Page 1 / Register 84-86: Reserved Registers - 0x00 / 0x01 / 0x54-0x56 (B0_P1_R84-86)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved.

Book 0 / Page 1 / Register 87: GPIO Pin 1 Register - 0x00 / 0x01 / 0x57 (B0_P1_R87)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D1RESERVEDR/W0000 000Reserved. Write only reset values.
D0GPO_BO_MODER/W00: Use R88,R89 to directly drive output on respective pins
1: Use DSP port to drive outputs on respective pins

Book 0 / Page 1 / Register 88: GPIO Pin 2 Register - 0x00 / 0x01 / 0x58 (B0_P1_R88)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7GPIO8_BOVR/W0GPIO8 general purpose output value is
0: Low(0)
1: High(1)
D6GPIO7_BOVR/W0GPIO7 general purpose output value is
0: Low(0)
1: High(1)
D5GPIO6_BOVR/W0GPIO6 general purpose output value is
0: Low(0)
1: High(1)
D4GPIO5_BOVR/W0GPIO5 general purpose output value is
0: Low(0)
1: High(1)
D3GPIO4_BOVR/W0GPIO4 general purpose output value is
0: Low(0)
1: High(1)
D2GPIO3_BOVR/W0GPIO3 General Purpose Output Value
0: Low(0)
1: High(1)
D1GPIO2_BOVR/W0GPIO2 General Purpose Output Valuet
0: Low(0)
1: High(1)
D0GPIO1_BOVR/W0GPIO1 General Purpose Output Value
0: Low(0)
1: High(1)

Book 0 / Page 1 / Register 89: GPIO Pin 3 Register - 0x00 / 0x01 / 0x59 (B0_P1_R89)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D2RESERVEDR/W0000 00Reserved. Write only reset values.
D1GPIO10_BOVR/W0GPIO10 general purpose output value is
0: Low(0)
1: High(1)
D0GPIO9_BOVR/W0GPIO9 general purpose output value is
0: Low(0)
1: High(1)

Book 0 / Page 1 / Register 90-107: Reserved Registers - 0x00 / 0x01 / 0x5A-0x6B (B0_P1_R84-86)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved. Write only reset values.

Book 0 / Page 1 / Register 108: Interrupt Control 1 Register - 0x00 / 0x01 / 0x6C (B0_P1_R108)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D4INT_OVER_IR/W000Speaker over-current flag is
000: not used in the generation of pin interrupt
001: used in the generation of INT1 interrupt
010: used in the generation of INT2 interrupt
011: used in the generation of INT3 interrupt
100: used in the generation of INT4 interrupt
101-111: Reserved
D3RESERVEDR/W0Reserved. Write only reset values.
D2-D0INT_OVER_VR/W000Speaker over-voltage flag is
000: not used in the generation of pin interrupt
001: used in the generation of INT1 interrupt
010: used in the generation of INT2 interrupt
011: used in the generation of INT3 interrupt
100: used in the generation of INT4 interrupt
101-111: Reserved

Book 0 / Page 1 / Register 109: Interrupt Control 2 Register - 0x00 / 0x01 / 0x6D (B0_P1_R109)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D4INT_CLK_ERR1R/W000Clock error detect 1 flag is
000: not used in the generation of pin Interrupt
001: used in the generation of INT1 Interrupt
010: used in the generation of INT2 Interrupt
011: used in the generation of INT3 Interrupt
100: used in the generation of INT4 Interrupt
101-111: Reserved
D3RESERVEDR/W0Reserved. Write only reset values.
D2-D0INT_OVER_TEMPR/W0Over-temperature flag is
000: not used in the generation of pin Interrupt
001: used in the generation of INT1 interrupt
010: used in the generation of INT2 interrupt
011: used in the generation of INT3 interrupt
100: used in the generation of INT4 interrupt
101-111: Reserved

Book 0 / Page 1 / Register 110: Interrupt Control 3 Register - 0x00 / 0x01 / 0x6E (B0_P1_R110)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D4INT_BROWNOUTR/W000Brownout flag is
000: not used in the generation of pin Interrupt
001: used in the generation of INT1 Interrupt
010: used in the generation of INT2 Interrupt
011: used in the generation of INT3 Interrupt
100: used in the generation of INT4 Interrupt
101-111: Reserved
D3RESERVEDR/W0Reserved. Write only reset values.
D2-D0INT_CLK_ERR2R/W000Clock error detect 2 flag is
000: not used in the generation of pin Interrupt
001: used in the generation of INT1 Interrupt
010: used in the generation of INT2 Interrupt
011: used in the generation of INT3 Interrupt
100: is used in the generation of INT4 Interrupt
101-111: Reserved

Book 0 / Page 1 / Register 111: Interrupt Control 4 Register - 0x00 / 0x01 / 0x6F (B0_P1_R111)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D4INT_SAR_DONER/W000SAR complete flag is
000: not used in the generation of pin Interrupt
001: used in the generation of INT1 Interrupt
010: used in the generation of INT2 Interrupt
011: used in the generation of INT3 Interrupt
100: used in the generation of INT4 Interrupt
101-111: Reserved
D3-D0RxxxxReserved. Write only reset values.

Book 0 / Page 1 / Register 112: Interrupt Control 5 Register - 0x00 / 0x01 / 0x70 (B0_P1_R112)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D4INT_DSP1R/W000DSP output interrupt 1 flag is
000: not used in the generation of pin Interrupt
001: used in the generation of INT1 Interrupt
010: used in the generation of INT2 Interrupt
011: used in the generation of INT3 Interrupt
100: used in the generation of INT4 Interrupt
101-111: Reserved
D3RESERVEDR/W0Reserved. Write only reset values.
D2-D0INT_DSP2R/W000DSP output interrupt 2 flag is
000: not used in the generation of pin Interrupt
001: used in the generation of INT1 Interrupt
010: used in the generation of INT2 Interrupt
011: used in the generation of INT3 Interrupt
100: used in the generation of INT4 Interrupt
101-111: Reserved

Book 0 / Page 1 / Register 113: Interrupt Control 6 Register - 0x00 / 0x01 / 0x71 (B0_P1_R113)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D4INT_DSP3R/W000DSP output interrupt 3 flag is
000: not used in the generation of pin Interrupt
001: used in the generation of INT1 Interrupt
010: used in the generation of INT2 Interrupt
011: used in the generation of INT3 Interrupt
100: used in the generation of INT4 Interrupt
101-111: Reserved
D3RESERVEDR/W0Reserved. Write only reset values.
D2-D0INT_DSP4R/W000DSP output interrupt 4 flag is
000: not used in the generation of pin Interrupt
001: used in the generation of INT1 Interrupt
010: used in the generation of INT2 Interrupt
011: used in the generation of INT3 Interrupt
100: used in the generation of INT4 Interrupt
101-111: Reserved

Book 0 / Page 1 / Register 114-127: Reserved Register - 0x00 / 0x01 / 0x72-0x7F (B0_P1_R127)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 Page 2

Book 0 / Page 2 / Register 0: Page Select Register - 0x00 / 0x02 / 0x00 (B0_P0_R0)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0PAGER/W0000 0000Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table for details.

Book 0 / Page 2 / Register 1-5: Reserved Register - 0x00 / 0x02 / 0x01-0x05 (B0_P1_R1-5)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 2 / Register 6: Ramp Generator Frequency Register - 0x00 / 0x02 / 0x06 (B0_P2_R6)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D5RESERVEDR/W000Reserved. Write only reset values.
D4RAMP_FREQR/W0Ramp Generator Frequency
00: 384kHz ramp_sel_res_freq = 0), Use this for Fs of 48ksps and its multiples
01: 352.8kHz, Use this for Fs of 44.1ksps and its multiples
D3-D0RESERVEDR/W0000Reserved. Write only reset values.

Book 0 / Page 2 / Register 7-23: Reserved Register - 0x00 / 0x02 / 0x07-0x17 (B0_P1_R7-23)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 0 / Page 2 / Register 24: Inrush Optimization 1 Register - 0x00 / 0x02 / 0x18 (B0_P2_R24)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6RESERVEDR/W00Reserved. Write only reset values.
D5-D3INRUSH1R/W101Inrush Current Optimization 1
000: Class-H operation inrush current optimization for boost
101 Not Recommended
Other: Reserved
D2-D0INRUSH2R/W101Inrush Current Optimization 2
000: Class-H operation inrush current optimization for boost
101 Not Recommended
Other: Reserved

Book 0 / Page 2 / Register 25: Inrush Optimization 2 Register - 0x00 / 0x02 / 0x19 (B0_P2_R25)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6RESERVEDR/W00Reserved. Write only reset values.
D5-D3INRUSH3R/W101Inrush Current Optimization 3
000: Class-H operation inrush current optimization for boost
101 Not Recommended
Other: Reserved
D2-D0INRUSH4R/W101Inrush Current Optimization 4
000: Class-H operation inrush current optimization for boost
101 Not Recommended
Other: Reserved

Book 0 / Page 2 / Register 26: Inrush Optimization 3 Register - 0x00 / 0x02 / 0x1A (B0_P2_R25)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6RESERVEDR/W00Reserved. Write only reset values.
D5-D3INRUSH5R/W101Inrush Current Optimization 5
000: Class-H operation inrush current optimization for boost
101 Not Recommended
Other: Reserved
D2-D0INRUSH6R/W101Inrush Current Optimization 6
000: Class-H operation inrush current optimization for boost
101 Not Recommended
Other: Reserved

Book 0 / Page 2 / Register 27: Inrush Optimization 4 Register - 0x00 / 0x02 / 0x1B (B0_P2_R25)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6RESERVEDR/W00Reserved. Write only reset values.
D5-D3INRUSH7R/W101Inrush Current Optimization 7
000: Class-H operation inrush current optimization for boost
101 Not Recommended
Other: Reserved
D2-D0INRUSH8R/W101Inrush Current Optimization 8
000: Class-H operation inrush current optimization for boost
101 Not Recommended
Other: Reserved

Book 0 / Page 2 / Register 28-127: Reserved Register - 0x00 / 0x02 / 0x1C-0x7F (B0_P1_R28-127)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 100 Page 0

Book 100 / Page 0 / Register 0: Page Select Register - 0x64 / 0x00 / 0x00 (B100_P0_R0)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0PAGER/W0000 0000Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table for details.

Book 100 / Page 0 / Register 1: DAC Interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0DAC_RATIOR/W0000 1000DAC Interpolation ratio outside DSP is
0000 0000: 256
0000 0001: 1
0000 0001: 2
...
1111 1110: 254
1111 1111: 255

Book 100 / Page 0 / Register 2: ADC interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6RESERVEDR/W00Reserved. Write only reset values.
D5-D0ADC_RATIOR/W00 0000ADC interpolation ratio outside DSP is
00 0000: 64
00 0001: 1
00 0001: 2
...
10 0101: 37
10 0110: 38 (maximum ratio supported for Isense/Vsense)
10 0111: 39 (supported only for PDM audio input)
10 1000: 40 (supported only for PDM audio input)
10 1001: 41 (supported only for PDM audio input)
10 1010: 42 (supported only for PDM audio input)
10 1011: 43 (supported only for PDM audio input)
10 1100: 44 (supported only for PDM audio input)
10 1101: 45 (supported only for PDM audio input)

Book 100 / Page 0 / Register 3-6: Reserved Register - 0x64 / 0x00 / 0x03-0x06 (B100_P0_R3-6)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved.

Book 100 / Page 0 / Register 7: DSP Mute Register - 0x64 / 0x00 / 0x07 (B100_P0_R7)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4RESERVEDR/W0000Reserved. Write only reset values.
D3PDM_MUTER/W1PDM soft mute is
0: un-mute
1: mute
D2VSNS_MUTER/W1Vsense soft mute is
0: un-mute
1: mute
D1ISNS_MUTER/W1Isense soft mute is
0: un-mute
1: mute
D0SPK_MUTER/W1Class-D soft mute is
0: un-mute
1: mute

Book 100 / Page 0 / Register 8-15: Reserved Register - 0x64 / 0x00 / 0x08-0x0F (B100_P0_R8-15)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 100 / Page 0 / Register 16: Interrupt 1 DSP Register - 0x64 / 0x00 / 0x10 (B100_P0_R16)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7INT1_POLR/W0ISR1 interrupt polarity is
0: Active High
1: Active Low
D6INT1_TRGR/W0ISR1 interrupt is
0: Level sensitive
1: Edge sensitive
D4-D0INT1_PATHR/W00000ISR1 interrupt input to DSP is
0 0000: disabled
0 0001: GPIO1
0 0010: GPIO2
0 0011: GPIO3
0 0100: GPIO4
0 0101: GPIO5
0 0110: GPIO6
0 0111: GPIO7
0 1000: GPIO8
0 1001: GPIO9
0 1010: GPIO10
0 1011: Reserved
0 1100: Reserved
0 1101: GPI1
0 1110: GPI2
0 1111: GPI3
others: Reserved

Book 100 / Page 0/ Register 17: Interrupt 2 DSP Register - 0x64 / 0x00 / 0x11 (B100_P0_R17)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7INT2_POLR/W0ISR2 interrupt polarity is
0: Active high
1: Active low
D6INT2_TRGR/W0ISR2 interrupt is
0: Level sensitive
1: Edge sensitive
D4-D0INT2_PATHR/W00000ISR2 interrupt input to DSP is
0 0000: disabled
0 0001: GPIO1
0 0010: GPIO2
0 0011: GPIO3
0 0100: GPIO4
0 0101: GPIO5
0 0110: GPIO6
0 0111: GPIO7
0 1000: GPIO8
0 1001: GPIO9
0 1010: GPIO10
0 1011: Reserved
0 1100: Reserved
0 1101: GPI1
0 1110: GPI2
0 1111: GPI3
others: Reserved

Book 100 / Page 0 / Register 18: Condition 1 DSP Register - 0x64 / 0x00 / 0x12 (B100_P0_R18)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7COND1_POLR/W0COND1 interrupt polarity is
0: Active high
1: Active low
D6COND1_TRGR/W0COND1 interrupt is
0: Level sensitive
1: Edge sensitive
D4-D0COND1_PATHR/W00000COND1 interrupt input to DSP is
0 0000: disabled
0 0001: GPIO1
0 0010: GPIO2
0 0011: GPIO3
0 0100: GPIO4
0 0101: GPIO5
0 0110: GPIO6
0 0111: GPIO7
0 1000: GPIO8
0 1001: GPIO9
0 1010: GPIO10
0 1011: Reserved
0 1100: Reserved
0 1101: GPI1
0 1110: GPI2
0 1111: GPI3
others: Reserved

Book 100/ Page 0 / Register 19: Condition 2 DSP Register - 0x64 / 0x00 / 0x13 (B100_P0_R19)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7COND2_POLR/W0COND2 interrupt polarity is
0: Active High
1: Active Low
D6COND2_TRGR/W0COND2 interrupt is
0: Level Sensitive
1: Edge Sensitive
D4-D0COND2_PATHR/W00000COND2 Interrupt Input to DSP
0 0000: disabled
0 0001: GPIO1
0 0010: GPIO2
0 0011: GPIO3
0 0100: GPIO4
0 0101: GPIO5
0 0110: GPIO6
0 0111: GPIO7
0 1000: GPIO8
0 1001: GPIO9
0 1010: GPIO10
0 1011: Reserved
0 1100: Reserved
0 1101: GPI1
0 1110: GPI2
0 1111: GPI3
others: Reserved

Book 100 / Page 0 / Register 20: ISR and COND Control Register - 0x64 / 0x00 / 0x14 (B100_P0_R20)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7DSP_ISR3R/W0ISR3 interrupt input to DSP is
0: Low
1: High
D6DSP_ISR4R/W0ISR4 interrupt input to DSP is
0: Low
1: High
D5-D4RESERVEDR/W00Reserved. Write only reset values.
D3DSP_COND3R/W0COND3 interrupt input to DSP is
0: Low
1: High
D2DSP_COND4COND4 interrupt input to DSP is
0: Low
1: High
D1-D0RESERVEDR/W00Reserved. Write only reset values.

Book 100 / Page 0/ Register 21: DSP Control Register - 0x64 / 0x00 / 0x15 (B100_P0_R21)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6DSP_SPI_DLYR/W0 0: SPI read will have one frame (8-bit) delay while reading RAMs.
1: SPI read will always have one frame (8-bit) delay
D5DSP_APAGER/W0Auto increment page for non-zero book is
0: Enable
1: Disable
D4-D0RESERVEDR/W0 0000Reserved. Write only reset values.

Book 100 / Page 0 / Register 22-26: Reserved Register - 0x64 / 0x00 / 0x16-0x1A (B100_P0_R22-26)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 100 / Page 0 / Register 27:PLL CLKIN Divider Register - 0x64 / 0x00 / 0x1B (B100_P0_R27)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6RESERVEDR/W00Reserved. Write only reset values.
D5-D0PLL_PDIVR/W00 0001PLL_CLKIN divider (generates input clock for PLL P-divider) is
00 0000: 64
00 0001: 1
00 0001: 2
...
11 1110: 62
11 1111: 63

Book 100 / Page 0 / Register 28:PLL J-VAL Divider Register - 0x64 / 0x00 / 0x1C (B100_P0_R28)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7PLL_LOWR/W0PLL low input frequency is
0: should be set when PLL CLKIN divider output is greater than 1MHz
1: should be set when PLL CLKIN divider output is less than 1MHz
D6-D0PLL_JDIVR/W00 0100PLL J multiplier is
00 0000: Reserved
00 0001: 1
00 0010: 2
...
11 1110: 62
11 1111: 63

Book 100 / Page 0 / Register 29:PLL D-VAL Divider 2 Register - 0x64 / 0x00 / 0x1D (B100_P0_R29)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W0Reserved. Write only reset values.
D6-D0PLL_DVAL2R/W000 0000PLL D Factional Multiplier D(13:8)

Book 100 / Page 0 / Register 30:PLL D-VAL Divider 1 Register - 0x64 / 0x00 / 0x1E (B100_P0_R30)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0PLL_DVAL1R/W0000 0000PLL D Factional Multiplier D(7:0)

Book 100 / Page 0 / Register 31:DSP Clock Register - 0x64 / 0x00 / 0x1F (B100_P0_R31)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6RESERVEDR/W00Reserved. Write only reset values.
D5DSP_CLKR/W0DSP clock is generated from
0: output of N_VAL divider in B100_P0_R32
1: directly from PLL Clock
D4-D3MDAC_CLKR/W00MDAC and MADC is clock divider input is
00: NDIV_CLK (N-divider output)
01: MCLK_GPI2. This can be used only if MCLK is multiple of 8*64*Fs or 4*64*Fs(with 48-52% duty-cycle)
10: ICC_GPIO9. This can be used only if MCLK is multiple of 8*64*Fs or 4*64*Fs(with 48-52% duty-cycle)
11: Reserved
D2-D1BOOST_CLKR/W00Boost and Charge-pump divider input is
00: NDIV_CLK (N-divider output)
01: MCLK_GPI2.
10: ICC_GPIO9.
11: Reserved
D0RESERVEDR/W0Reserved. Write only reset values.

Book 100 / Page 0 / Register 32: N-VAL Divider Register - 0x64 / 0x00 / 0x20 (B100_P0_R32)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0N_DIVR/W0000 0001N divider is
0000 0000: 128
0000 0001: 1
0000 0010: 2
...
1111 1110: 126
1111 1111: 127

Book 100 / Page 0 / Register 33: MDAC-VAL Divider Register - 0x64 / 0x00 / 0x21 (B100_P0_R33)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0MDAC_DIVR/W0000 0100DAC divider is
0000 0000: 128
0000 0001: 1
0000 0010: 2
...
1111 1110: 126
1111 1111: 127

Book 100 / Page 0 / Register 34: MADC-VAL Divider Register - 0x64 / 0x00 / 0x22 (B100_P0_R34)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RESERVEDR/W00Reserved. Write only reset values.
D6-D3MADC_DIV_PRER/W 0001ADC Divider pre is
0000: 16
0001: 1
0010: 2
...
1110: 14
1111: 15
D2-D0MADC_DIV_FINR/W 000ADC divider final (this divider configuration is used only if B100_P0_R42[7:6]=11) is
000: 8
001: 1
010: 2
...
110: 6
111: 7

Book 100 / Page 0 / Register 35-37: Reserved Register - 0x64 / 0x00 / 0x23-0x25 (B100_P0_R35-37)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved

Book 100 / Page 0 / Register 38: Charge-pump Clock Register - 0x64 / 0x00 / 0x26 (B100_P0_R38)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7CP_CLK_GENR/W0Charge pump clock generation is
0: Use internally generated oscillator clock
1: Use NDIV_CLK/MCLK_GPI2/ICC_GPIO9
D6-D5RESERVEDR/W00Reserved. Write only reset values.
D4-D0CP_CLK_DIVR/W0010Charge pump clock divider factor is
0 0000: 32
0 0001: 1
0 0010: 2
...
1 1110: 30
1 1111: 31

Book 100 / Page 0 / Register 39: Boost Clock Register - 0x64 / 0x00 / 0x27 (B100_P0_R39)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RMP_CLK_GENR/W0Boost clock generation uses
0: internally generated oscillator clock
1: NDIV_CLK/MCLK_GPI2/ICC_GPIO9
D6-D3BST_DIV_PRER/W0010Boost clock pre divider factor is
0000: 16
0001: 1
0010: 2
...
1110: 14
1111: 15
D2-D0BST_DIV_FINR/W 011ADC divider final (this divider configuration is used only if B100_P0_R42[7:6]=11) is
000: 8
001: 1
010: 2
...
110: 6
111: 7

Book 100 / Page 0 / Register 40: Ramp Clock 1 Register - 0x64 / 0x00 / 0x28 (B100_P0_R40)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7RMP_CLK_GENR/W0Ramp clock generation is
0: internally generated
1: from DAC modulator clock (Refer to divider settings in B100_P0_R43-44)
D6-D0RESERVEDR/W000 0000Reserved. Write only reset values.

Book 100 / Page 0 / Register 41-42: Reserved Register - 0x64 / 0x00 / 0x29-0x2A (B100_P0_R41-42)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved.

Book 100 / Page 0 / Register 43: Ramp Clock 2 Register - 0x64 / 0x00 / 0x2B (B100_P0_R43)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D3RESERVEDR/W0000 0Reserved. Write only reset values.
D2-D0RMP_CLK_MSBR/W000Ramp Clock Divider [10:8]

Book 100 / Page 0 / Register 44: Ramp Clock 3 Register - 0x64 / 0x00 / 0x2C (B100_P0_R44)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RMP_CLK_LSBR/W000Ramp Clock Divider [7:0]

Book 100 / Page 0/ Register 45-126: Reserved Register - 0x64 / 0x01 / 0x2D-0x7E (B100_P0_R45-126)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0RESERVEDRxxxx xxxxReserved.

Book 100 / Page 0 / Register 127: Book Selection Register - 0x64 / 0x00 / 0x7F (B100_P0_R127)

BITFIELDREAD/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0BOOKR/W0110 01000-255: Selects the Register Book for next read or write command.