ZHCSFY2A August 2015  – November 2016 TAS2555

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 SPI Timing Requirements
    8. 7.8 I2S/LJF/RJF Timing in Master Mode
    9. 7.9 I2S/LJF/RJF Timing in Slave Mode
    10. 7.10DSP Timing in Master Mode
    11. 7.11DSP Timing in Slave Mode
    12. 7.12Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1 General I2C Operation
      2. 9.3.2 Single-Byte and Multiple-Byte Transfers
      3. 9.3.3 Single-Byte Write
      4. 9.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.3.5 Single-Byte Read
      6. 9.3.6 Multiple-Byte Read
      7. 9.3.7 General SPI Operation
      8. 9.3.8 Class-D Edge Rate Control
      9. 9.3.9 Battery Tracking AGC
      10. 9.3.10Configurable Boost Current Limit (ILIM)
        1. 9.3.10.1Fault Protection
          1. 9.3.10.1.1OverCurrent
          2. 9.3.10.1.2Analog Undervoltage
          3. 9.3.10.1.3Overtemperature
          4. 9.3.10.1.4Clocking Faults
        2. 9.3.10.2Brownout
        3. 9.3.10.3Spread Spectrum vs Synchronized
        4. 9.3.10.4IRQs and Flags
        5. 9.3.10.5Software Reset
        6. 9.3.10.6PurePath Console 3 Software TAS2555 Application
    4. 9.4Device Functional Modes
      1. 9.4.1Audio Digital I/O Interface
        1. 9.4.1.1Right-Justified Mode (RJF)
        2. 9.4.1.2Left-Justified Mode (LJF)
        3. 9.4.1.3I2S Mode
        4. 9.4.1.4DSP Mode
      2. 9.4.2TDM Mode
      3. 9.4.3Device Digital Processing Modes
        1. 9.4.3.1ROM Mode 1
        2. 9.4.3.2ROM Mode 2
        3. 9.4.3.3SmartAmp Mode
      4. 9.4.4Low Power Sleep Mode
    5. 9.5Programming
      1. 9.5.1Code Loading and CRC check
      2. 9.5.2Device Power Up, Power Down, Mute and Un-mute Sequence
  10. 10Applications and Implementation
    1. 10.1Application Information
    2. 10.2Typical Applications
      1. 10.2.1Design Requirements
        1. 10.2.1.1Detailed Design Procedure
          1. 10.2.1.1.1Mono/Stereo Configuration
          2. 10.2.1.1.2Boost Converter Passive Devices
          3. 10.2.1.1.3EMI Passive Devices
          4. 10.2.1.1.4Miscellaneous Passive Devices
      2. 10.2.2Application Performance Plots
    3. 10.3Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1Power Supplies
    2. 11.2Power Supply Sequencing
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Register Map
    1. 13.1Register Map Summary
    2. 13.2 Book 0 Page 0
      1. 13.2.1 Book 0 / Page 0 / Register 0: Page Select Register - 0x00 / 0x00 / 0x00 (B0_P0_R0)
      2. 13.2.2 Book 0 / Page 0 / Register 1: Software Reset Register - 0x00 / 0x00 / 0x01 (B0_P0_R1)
      3. 13.2.3 Book 0 / Page 0 / Register 2-3: Reserved Registers - 0x00 / 0x00 / 0x02-0x03 (B0_P0_R2-3)
      4. 13.2.4 Book 0 / Page 0 / Register 4: Power Control Register - 0x00 / 0x00 / 0x04 (B0_P0_R4)
      5. 13.2.5 Book 0 / Page 0 / Register 5: Power Control Register 2 - 0x00 / 0x00 / 0x05 (B0_P0_R5)
      6. 13.2.6 Book 0 / Page 0 / Register 6: Speaker Control Register - 0x00 / 0x00 / 0x06 (B0_P0_R6)
      7. 13.2.7 Book 0 / Page 0 / Register 7: Mute Register - 0x00 / 0x00 / 0x07 (B0_P0_R7)
      8. 13.2.8 Book 0 / Page 0 / Register 8: Channel Control Register - 0x00 / 0x00 / 0x08 (B0_P0_R8)
      9. 13.2.9 Book 0 / Page 0 / Register 9-31: Reserved Registers - 0x00 / 0x00 / 0x09-0x1F (B0_P0_R9-31)
      10. 13.2.10Book 0 / Page 0 / Register 32: CRC Checksum Register - 0x00 / 0x00 / 0x20 (B0_P0_R32)
      11. 13.2.11Book 0 / Page 0 / Register 33: Checksum Reset Register - 0x00 / 0x00 / 0x21 (B0_P0_R33)
      12. 13.2.12Book 0 / Page 0 / Register 34: Device DSP Mode Register - 0x00 / 0x00 / 0x22 (B0_P0_R34)
      13. 13.2.13Book 0 / Page 0 / Register 35-39: Reserved Registers - 0x00 / 0x00 / 0x23-0x27 (B0_P0_R35-R39)
      14. 13.2.14Book 0 / Page 0 / Register 40: Class-D SSM Mode Register - 0x00 / 0x00 / 0x28 (B0_P0_R40)
      15. 13.2.15Book 0 / Page 0 / Register 41: Reserved Registers - 0x00 / 0x00 / 0x29 (B0_P0_R41)
      16. 13.2.16Book 0 / Page 0 / Register 42: Digital Playback Control Register - 0x00 / 0x00 / 0x2A (B0_P0_R42)
      17. 13.2.17Book 0 / Page 0 / Register 43: Current Limit Register - 0x00 / 0x00 / 0x2B (B0_P0_R43)
      18. 13.2.18Book 0 / Page 0 / Register 44: Clock Error Control 1 Register - 0x00 / 0x00 / 0x2C (B0_P0_R44)
      19. 13.2.19Book 0 / Page 0 / Register 45: Clock Error Control 2 Register - 0x00 / 0x00 / 0x2D (B0_P0_R45)
      20. 13.2.20Book 0 / Page 0 / Register 46: Clock Error Control 3 Register - 0x00 / 0x00 / 0x2E (B0_P0_R46)
      21. 13.2.21Book 0 / Page 0 / Register 47-99: Reserved Registers - 0x00 / 0x00 / 0x2F-0x63 (B0_P0_R47-R99)
      22. 13.2.22Book 0 / Page 0 / Register 100: Power Up Flag Register - 0x00 / 0x00 / 0x64 (B0_P0_R100)
      23. 13.2.23Book 0 / Page 0 / Register 101-103: Reserved Registers - 0x00 / 0x00 / 0x65-0x67 (B0_P0_R101-R103)
      24. 13.2.24Book 0 / Page 0 / Register 104: Interrupt Flags DAC & OCP/OTP Sticky Register - 0x00 / 0x00 / 0x68 (B0_P0_R104)
      25. 13.2.25Book 0 / Page 0 / Register 105-107: Reserved Registers - 0x00 / 0x00 / 0x69-0x6B (B0_P0_R105-R107)
      26. 13.2.26Book 0 / Page 0 / Register 108: DSP Interrupt Output Sticky Register - 0x00 / 0x00 / 0x6C (B0_P0_R108)
      27. 13.2.27Book 0 / Page 0 / Register 109-120: Reserved Registers - 0x00 / 0x00 / 0x6D-0x78 (B0_P0_R109-R120)
      28. 13.2.28Book 0 / Page 0 / Register 121: Power Modes Register - 0x00 / 0x00 / 0x79 (B0_P0_R121)
      29. 13.2.29Book 0 / Page 0 / Register 122-126: Reserved Registers - 0x00 / 0x00 / 0x7A-0x7E (B0_P0_R122-R126)
      30. 13.2.30Book 0 / Page 0 / Register 127: Book Selection Register - 0x00 / 0x00 / 0x7F (B0_P0_R127)
    3. 13.3 Book 0 Page 1
      1. 13.3.1 Book 0 / Page 1 / Register 0: Page Select Register - 0x00 / 0x01 / 0x00 (B0_P1_R0)
      2. 13.3.2 Book 0 / Page 1 / Register 1: ASI1 DAC Format Register - 0x00 / 0x01 / 0x01 (B0_P1_R1)
      3. 13.3.3 Book 0 / Page 1 / Register 2: ASI1 ADC Format Register - 0x00 / 0x01 / 0x02 (B0_P1_R2)
      4. 13.3.4 Book 0 / Page 1 / Register 3: ASI1 Offset Register - 0x00 / 0x00 / 0x03 (B0_P1_R3)
      5. 13.3.5 Book 0 / Page 1 / Register 4-6: Reserved Registers - 0x00 / 0x01 / 0x04-0x06 (B0_P1_R4-6)
      6. 13.3.6 Book 0 / Page 1 / Register 7: ASI1 ADC Path Register - 0x00 / 0x01 / 0x07 (B0_P1_R7)
      7. 13.3.7 Book 0 / Page 1 / Register 8: ASI1 DAC BCLK Register - 0x00 / 0x01 / 0x08 (B0_P1_R8)
      8. 13.3.8 Book 0 / Page 1 / Register 9: ASI1 DAC WCLK Register - 0x00 / 0x01 / 0x09 (B0_P1_R9)
      9. 13.3.9 Book 0 / Page 1 / Register 10: ASI1 ADC BCLK Register - 0x00 / 0x01 / 0x0A (B0_P1_R10)
      10. 13.3.10Book 0 / Page 1 / Register 11: ASI1 ADC WCLK Register - 0x00 / 0x01 / 0x0B (B0_P1_R11)
      11. 13.3.11Book 0 / Page 1 / Register 12: ASI1 DIN/DOUT MUX Register - 0x00 / 0x01 / 0x0C (B0_P1_R12)
      12. 13.3.12Book 0 / Page 1 / Register 13: ASI1 BDIV Clock Select Register - 0x00 / 0x01 / 0x0D (B0_P1_R13)
      13. 13.3.13Book 0 / Page 1 / Register 14: ASI1 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x0E (B0_P1_R14)
      14. 13.3.14Book 0 / Page 1 / Register 15: ASI1 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x0F (B0_P1_R15)
      15. 13.3.15Book 0 / Page 1 / Register 16: ASI1 DAC Clock Output Register - 0x00 / 0x01 / 0x10 (B0_P1_R16)
      16. 13.3.16Book 0 / Page 1 / Register 17: ASI1 ADC Clock Output Register - 0x00 / 0x01 / 0x11 (B0_P1_R17)
      17. 13.3.17Book 0 / Page 1 / Register 18-20: Reserved Registers - 0x00 / 0x01 / 0x12-0x14 (B0_P1_R18-20)
      18. 13.3.18Book 0 / Page 1 / Register 21: ASI2 DAC Format Register - 0x00 / 0x01 / 0x15 (B0_P1_R21)
      19. 13.3.19Book 0 / Page 1 / Register 22: ASI2 ADC Format Register - 0x00 / 0x01 / 0x16 (B0_P1_R22)
      20. 13.3.20Book 0 / Page 1 / Register 23: ASI2 Offset Register - 0x00 / 0x01 / 0x17 (B0_P1_R23)
      21. 13.3.21Book 0 / Page 1 / Register 24-26: Reserved Registers - 0x00 / 0x01 / 0x18-0x1A (B0_P1_R24-26)
      22. 13.3.22Book 0 / Page 1 / Register 27: ASI2 ADC Path Register - 0x00 / 0x01 / 0x1B (B0_P1_R27)
      23. 13.3.23Book 0 / Page 1 / Register 28: ASI2 DAC BCLK Register - 0x00 / 0x01 / 0x1C (B0_P1_R28)
      24. 13.3.24Book 0 / Page 1 / Register 29: ASI2 DAC WCLK Register - 0x00 / 0x01 / 0x1D (B0_P1_R29)
      25. 13.3.25Book 0 / Page 1 / Register 30: ASI2 ADC BCLK Register - 0x00 / 0x01 / 0x1E (B0_P1_R30)
      26. 13.3.26Book 0 / Page 1 / Register 31: ASI2 ADC WCLK Register - 0x00 / 0x01 / 0x1F (B0_P1_R31)
      27. 13.3.27Book 0 / Page 1 / Register 32: ASI2 DIN/DOUT MUX - 0x00 / 0x01 / 0x20 (B0_P1_R32)
      28. 13.3.28Book 0 / Page 1 / Register 33: ASI2 BDIV Clock Select Register - 0x00 / 0x01 / 0x21 (B0_P1_R33)
      29. 13.3.29Book 0 / Page 1 / Register 34: ASI2 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x22 (B0_P1_R34)
      30. 13.3.30Book 0 / Page 1 / Register 35: ASI2 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x23 (B0_P1_R35)
      31. 13.3.31Book 0 / Page 1 / Register 36: ASI2 DAC Clock Output Register - 0x00 / 0x01 / 0x24 (B0_P1_R36)
      32. 13.3.32Book 0 / Page 1 / Register 37: ASI2 ADC Clock Output Register - 0x00 / 0x01 / 0x25 (B0_P1_R37)
      33. 13.3.33Book 0 / Page 1 / Register 38-60: Reserved Registers - 0x00 / 0x01 / 0x26-0x3C (B0_P1_R38-60)
      34. 13.3.34Book 0 / Page 1 / Register 61: BCLK1_GPIO1 Pin Register - 0x00 / 0x01 / 0x3D (B0_P1_R61)
      35. 13.3.35Book 0 / Page 1 / Register 62: WCLK1_GPIO2 Pin Register - 0x00 / 0x01 / 0x3E (B0_P1_R62)
      36. 13.3.36Book 0 / Page 1 / Register 63: DOUT1_GPIO3 Pin Register - 0x00 / 0x01 / 0x3F (B0_P1_R63)
      37. 13.3.37Book 0 / Page 1 / Register 64: IRQ_GPIO4 Pin Register - 0x00 / 0x01 / 0x40 (B0_P1_R64)
      38. 13.3.38Book 0 / Page 1 / Register 65: BCLK2_GPIO5 Pin Register - 0x00 / 0x01 / 0x41 (B0_P1_R65)
      39. 13.3.39Book 0 / Page 1 / Register 66: WCLK2_GPIO6 Pin Register - 0x00 / 0x01 / 0x42 (B0_P1_R66)
      40. 13.3.40Book 0 / Page 1 / Register 67: DOUT2_GPIO7 Pin Register - 0x00 / 0x01 / 0x43 (B0_P1_R67)
      41. 13.3.41Book 0 / Page 1 / Register 68: DIN2_GPIO8 Pin Register - 0x00 / 0x01 / 0x44 (B0_P1_R68)
      42. 13.3.42Book 0 / Page 1 / Register 69: ICC_GPIO9 Pin(ICC_CLK) Register - 0x00 / 0x01 / 0x45 (B0_P1_R69)
      43. 13.3.43Book 0 / Page 1 / Register 70: ICC_GPIO10 Pin Register - 0x00 / 0x01 / 0x46 (B0_P1_R70)
      44. 13.3.44Book 0 / Page 1 / Register 71-76: Reserved Registers - 0x00 / 0x01 / 0x47-0x4C (B0_P1_R71-76)
      45. 13.3.45Book 0 / Page 1 / Register 77: GPI Pins Register - 0x00 / 0x01 / 0x4D (B0_P1_R77)
      46. 13.3.46Book 0 / Page 1 / Register 78: Reserved Register - 0x00 / 0x01 / 0x4E (B0_P1_R78)
      47. 13.3.47Book 0 / Page 1 / Register 79: GPIO HIZ CTRL1 Register - 0x00 / 0x01 / 0x4F (B0_P1_R79)
      48. 13.3.48Book 0 / Page 1 / Register 80: GPIO HIZ CTRL2 Register - 0x00 / 0x01 / 0x50 (B0_P1_R80)
      49. 13.3.49Book 0 / Page 1 / Register 81: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x51 (B0_P1_R81)
      50. 13.3.50Book 0 / Page 1 / Register 82: GPIO HIZ CTRL4 Register - 0x00 / 0x01 / 0x52 (B0_P1_R82)
      51. 13.3.51Book 0 / Page 1 / Register 83: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x53 (B0_P1_R83)
      52. 13.3.52Book 0 / Page 1 / Register 84-86: Reserved Registers - 0x00 / 0x01 / 0x54-0x56 (B0_P1_R84-86)
      53. 13.3.53Book 0 / Page 1 / Register 87: GPIO Pin 1 Register - 0x00 / 0x01 / 0x57 (B0_P1_R87)
      54. 13.3.54Book 0 / Page 1 / Register 88: GPIO Pin 2 Register - 0x00 / 0x01 / 0x58 (B0_P1_R88)
      55. 13.3.55Book 0 / Page 1 / Register 89: GPIO Pin 3 Register - 0x00 / 0x01 / 0x59 (B0_P1_R89)
      56. 13.3.56Book 0 / Page 1 / Register 90-107: Reserved Registers - 0x00 / 0x01 / 0x5A-0x6B (B0_P1_R84-86)
      57. 13.3.57Book 0 / Page 1 / Register 108: Interrupt Control 1 Register - 0x00 / 0x01 / 0x6C (B0_P1_R108)
      58. 13.3.58Book 0 / Page 1 / Register 109: Interrupt Control 2 Register - 0x00 / 0x01 / 0x6D (B0_P1_R109)
      59. 13.3.59Book 0 / Page 1 / Register 110: Interrupt Control 3 Register - 0x00 / 0x01 / 0x6E (B0_P1_R110)
      60. 13.3.60Book 0 / Page 1 / Register 111: Interrupt Control 4 Register - 0x00 / 0x01 / 0x6F (B0_P1_R111)
      61. 13.3.61Book 0 / Page 1 / Register 112: Interrupt Control 5 Register - 0x00 / 0x01 / 0x70 (B0_P1_R112)
      62. 13.3.62Book 0 / Page 1 / Register 113: Interrupt Control 6 Register - 0x00 / 0x01 / 0x71 (B0_P1_R113)
      63. 13.3.63Book 0 / Page 1 / Register 114-127: Reserved Register - 0x00 / 0x01 / 0x72-0x7F (B0_P1_R127)
    4. 13.4 Book 0 Page 2
      1. 13.4.1Book 0 / Page 2 / Register 0: Page Select Register - 0x00 / 0x02 / 0x00 (B0_P0_R0)
      2. 13.4.2Book 0 / Page 2 / Register 1-5: Reserved Register - 0x00 / 0x02 / 0x01-0x05 (B0_P1_R1-5)
      3. 13.4.3Book 0 / Page 2 / Register 6: Ramp Generator Frequency Register - 0x00 / 0x02 / 0x06 (B0_P2_R6)
      4. 13.4.4Book 0 / Page 2 / Register 7-23: Reserved Register - 0x00 / 0x02 / 0x07-0x17 (B0_P1_R7-23)
      5. 13.4.5Book 0 / Page 2 / Register 24: Inrush Optimization 1 Register - 0x00 / 0x02 / 0x18 (B0_P2_R24)
      6. 13.4.6Book 0 / Page 2 / Register 25: Inrush Optimization 2 Register - 0x00 / 0x02 / 0x19 (B0_P2_R25)
      7. 13.4.7Book 0 / Page 2 / Register 26: Inrush Optimization 3 Register - 0x00 / 0x02 / 0x1A (B0_P2_R25)
      8. 13.4.8Book 0 / Page 2 / Register 27: Inrush Optimization 4 Register - 0x00 / 0x02 / 0x1B (B0_P2_R25)
      9. 13.4.9Book 0 / Page 2 / Register 28-127: Reserved Register - 0x00 / 0x02 / 0x1C-0x7F (B0_P1_R28-127)
    5. 13.5 Book 100 Page 0
      1. 13.5.1 Book 100 / Page 0 / Register 0: Page Select Register - 0x64 / 0x00 / 0x00 (B100_P0_R0)
      2. 13.5.2 Book 100 / Page 0 / Register 1: DAC Interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
      3. 13.5.3 Book 100 / Page 0 / Register 2: ADC interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
      4. 13.5.4 Book 100 / Page 0 / Register 3-6: Reserved Register - 0x64 / 0x00 / 0x03-0x06 (B100_P0_R3-6)
      5. 13.5.5 Book 100 / Page 0 / Register 7: DSP Mute Register - 0x64 / 0x00 / 0x07 (B100_P0_R7)
      6. 13.5.6 Book 100 / Page 0 / Register 8-15: Reserved Register - 0x64 / 0x00 / 0x08-0x0F (B100_P0_R8-15)
      7. 13.5.7 Book 100 / Page 0 / Register 16: Interrupt 1 DSP Register - 0x64 / 0x00 / 0x10 (B100_P0_R16)
      8. 13.5.8 Book 100 / Page 0/ Register 17: Interrupt 2 DSP Register - 0x64 / 0x00 / 0x11 (B100_P0_R17)
      9. 13.5.9 Book 100 / Page 0 / Register 18: Condition 1 DSP Register - 0x64 / 0x00 / 0x12 (B100_P0_R18)
      10. 13.5.10Book 100/ Page 0 / Register 19: Condition 2 DSP Register - 0x64 / 0x00 / 0x13 (B100_P0_R19)
      11. 13.5.11Book 100 / Page 0 / Register 20: ISR and COND Control Register - 0x64 / 0x00 / 0x14 (B100_P0_R20)
      12. 13.5.12Book 100 / Page 0/ Register 21: DSP Control Register - 0x64 / 0x00 / 0x15 (B100_P0_R21)
      13. 13.5.13Book 100 / Page 0 / Register 22-26: Reserved Register - 0x64 / 0x00 / 0x16-0x1A (B100_P0_R22-26)
      14. 13.5.14Book 100 / Page 0 / Register 27:PLL CLKIN Divider Register - 0x64 / 0x00 / 0x1B (B100_P0_R27)
      15. 13.5.15Book 100 / Page 0 / Register 28:PLL J-VAL Divider Register - 0x64 / 0x00 / 0x1C (B100_P0_R28)
      16. 13.5.16Book 100 / Page 0 / Register 29:PLL D-VAL Divider 2 Register - 0x64 / 0x00 / 0x1D (B100_P0_R29)
      17. 13.5.17Book 100 / Page 0 / Register 30:PLL D-VAL Divider 1 Register - 0x64 / 0x00 / 0x1E (B100_P0_R30)
      18. 13.5.18Book 100 / Page 0 / Register 31:DSP Clock Register - 0x64 / 0x00 / 0x1F (B100_P0_R31)
      19. 13.5.19Book 100 / Page 0 / Register 32: N-VAL Divider Register - 0x64 / 0x00 / 0x20 (B100_P0_R32)
      20. 13.5.20Book 100 / Page 0 / Register 33: MDAC-VAL Divider Register - 0x64 / 0x00 / 0x21 (B100_P0_R33)
      21. 13.5.21Book 100 / Page 0 / Register 34: MADC-VAL Divider Register - 0x64 / 0x00 / 0x22 (B100_P0_R34)
      22. 13.5.22Book 100 / Page 0 / Register 35-37: Reserved Register - 0x64 / 0x00 / 0x23-0x25 (B100_P0_R35-37)
      23. 13.5.23Book 100 / Page 0 / Register 38: Charge-pump Clock Register - 0x64 / 0x00 / 0x26 (B100_P0_R38)
      24. 13.5.24Book 100 / Page 0 / Register 39: Boost Clock Register - 0x64 / 0x00 / 0x27 (B100_P0_R39)
      25. 13.5.25Book 100 / Page 0 / Register 40: Ramp Clock 1 Register - 0x64 / 0x00 / 0x28 (B100_P0_R40)
      26. 13.5.26Book 100 / Page 0 / Register 41-42: Reserved Register - 0x64 / 0x00 / 0x29-0x2A (B100_P0_R41-42)
      27. 13.5.27Book 100 / Page 0 / Register 43: Ramp Clock 2 Register - 0x64 / 0x00 / 0x2B (B100_P0_R43)
      28. 13.5.28Book 100 / Page 0 / Register 44: Ramp Clock 3 Register - 0x64 / 0x00 / 0x2C (B100_P0_R44)
      29. 13.5.29Book 100 / Page 0/ Register 45-126: Reserved Register - 0x64 / 0x01 / 0x2D-0x7E (B100_P0_R45-126)
      30. 13.5.30Book 100 / Page 0 / Register 127: Book Selection Register - 0x64 / 0x00 / 0x7F (B100_P0_R127)
  14. 14器件和文档支持
    1. 14.1文档支持
    2. 14.2社区资源
    3. 14.3商标
    4. 14.4静电放电警告
    5. 14.5Glossary
  15. 15机械、封装和可订购信息
    1. 15.1封装尺寸

Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TAS2555 device is a digital or analog input high efficiency Class-D audio power amplifier with advanced battery current management and an integrated Class-H boost converter. In auto passthrough mode, the Class-H boost converter generates the Class-D amplifier supply rail. During low Class-D output power, the boost improves efficiency by deactivating and connecting VBAT directly to the Class-D amplifier supply. When high power audio is required, the boost quickly activates to provide louder audio than a stand-alone amplifier connected directly to the battery. To enable load monitoring, the TAS2555 device constantly measures the current and voltage across the load and provides a digital stream of this information back to a processor.

Typical Applications

TAS2555 Apps_Diagram_Digital_Input.gif Figure 38. Typical Application - Digital Audio Input

Table 4. Recommended External Components

COMPONENTDESCRIPTIONSPECIFICATIONMINTYPMAXUNIT
L1Boost Converter Inductor Inductance, 20% Tolerance12.2µH
Saturation Current3.1A
L2, L3EMI Filter Inductors (optional). These are not recommended as it degrades THD+N performance. The TAS2555 device is a filter-less Class-D and does not require these bead inductors.Impedance at 100MHz120Ω
DC Resistance0.095Ω
DC Current2A
Size0402EIA
C1Boost Converter Input CapacitorCapacitance, 20% Tolerance10µF
C2Boost Converter Output CapacitorTypeX5R
Capacitance, 20% Tolerance2247µF
Rated Voltage16V
Capacitance at 8.5 V derating7µF
C3, C4EMI Filter Capacitors (optional, must use L2, L3 if C3, C4 used)Capacitance1nF

Design Requirements

For this design example, use the parameters shown in Table 5.

Table 5. Design Parameters

DESIGN PARAMETEREXAMPLE VALUE
Audio InputDigital Audio, I2S
Current and Voltage Data StreamDigital Audio, I2S
Mono or Stereo ConfigurationMono
Max Output Power at 1% THD+N3.8 W

Detailed Design Procedure

Mono/Stereo Configuration

In this application, the device is assumed to be operating in mono mode. See General I2C Operation for information on changing the I2C address of the TAS2555 device to support stereo operation. Mono or stereo configuration does not impact the device performance.

Boost Converter Passive Devices

The boost converter requires three passive devices that are labeled L1, C1 and C2 in Figure 38 and whose specifications are provided in Table 4. These specifications are based on the design of the TAS2555 and are necessary to meet the performance targets of the device. In particular, L1 should not be allowed to enter in the current saturation region. The saturation current for L1 should be > ILIM to deliver Class-D peak power.

Additionally, the ratio of L1/C2 (the derated value of C2 at 8.5 V should be used in this ratio) has to be lesser than 1/3 for boost stability. This 1/3 ratio should be maintained including the worst case variation of L1 and C2. To satisfy sufficient energy transfer, L1 must be >= 1µH at the boost switching frequency (~1.7 MHz). Using a 1µH will have more boost ripple than a 2.2µH but the PSRR should minimize the effect from the additional ripple. Finally, the minimum C2 (derated value at 8.5 V) should be > 3.3µF for Class-D power delivery specification.

EMI Passive Devices

The TAS2555 device supports edge-rate control to minimize EMI, but the system designer may want to include passive devices on the Class-D output devices. These passive devices that are labeled L2, L3, C3 and C4 in Figure 38 and their recommended specifications are provided in Table 4. If C3 and C4 are used, they must be placed after L2 and L3 respectively to maintain the stability of the output stage.

Miscellaneous Passive Devices

  • VREG Capacitor: Must be 10 nF to meet boost and Class-D power delivery and efficiency specs.

Application Performance Plots

TAS2555 D001_SLASE69_TAS2555.gif
Freq = 1kHz VBAT = 3.6 V, AVDD = IOVDD = 1.8 V, RESET = IOVDD, RL = 8 Ω + 33 µH, I2S digital input, ROM mode 1
Figure 39. THD+N vs Output Power (8 Ω) for Digital Input

Initialization Set Up

To configure the TAS2555 device, follow these steps.

  1. Bring-up the power supplies as in Power Supply Sequencing.
  2. Set the /RESET terminal to HIGH.
  3. Follow the software sequence in section Device Power Up, Power Down, Mute and Un-mute Sequence