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SN75LVDS84

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FlatLink™ 变送器

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SN75LVDS84

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产品详情

Protocols Catalog Rating Catalog Operating temperature range (°C) 0 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) 0 to 70
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • 21:3 Data Channel Compression at up to 163 Million Bytes per Second Throughput
  • Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI
  • 21 Data Channels Plus Clock-In Low-Voltage TTL and 3 Data Channels Plus Clock-Out Low-Voltage Differential
  • Operates From a Single 3.3-V Supply and 250 mW (Typ)
  • 5-V Tolerant Data Inputs
  • ESD Protection Exceeds 6 kV
  • SN75LVDS84 Has Falling-Clock Edge-Triggered Inputs
  • Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range:
    • 31 MHz to 68 MHz
  • No External Components Required for PLL
  • Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Improved Replacement for the DS90C561

FlatLink is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
  • 21:3 Data Channel Compression at up to 163 Million Bytes per Second Throughput
  • Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI
  • 21 Data Channels Plus Clock-In Low-Voltage TTL and 3 Data Channels Plus Clock-Out Low-Voltage Differential
  • Operates From a Single 3.3-V Supply and 250 mW (Typ)
  • 5-V Tolerant Data Inputs
  • ESD Protection Exceeds 6 kV
  • SN75LVDS84 Has Falling-Clock Edge-Triggered Inputs
  • Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range:
    • 31 MHz to 68 MHz
  • No External Components Required for PLL
  • Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Improved Replacement for the DS90C561

FlatLink is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

The SN75LVDS84 FlatLink™ transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86.

When transmitting, data bits D0–D20 are each loaded into registers of the SN75LVDS84 on the falling edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS84 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The SN75LVDS84 is characterized for operation over ambient free-air temperatures of 0°C to 70°C.

The SN75LVDS84 FlatLink™ transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86.

When transmitting, data bits D0–D20 are each loaded into registers of the SN75LVDS84 on the falling edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS84 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The SN75LVDS84 is characterized for operation over ambient free-air temperatures of 0°C to 70°C.
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类型 标题 下载最新的英语版本 日期
* 数据表 Flatlink Transmitters 数据表 (Rev. D) 2007年 11月 6日
应用手册 High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 2018年 11月 9日
应用手册 Flatlink Data Transmission System Design Overview (Rev. A) 2001年 6月 1日
应用手册 Time Budgeting of the Flatlink Interface Application Report 1997年 6月 11日

设计和开发

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仿真模型

SN75LVDS84 IBIS Model

SLLC106.ZIP (5 KB) - IBIS Model
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用户指南: PDF
英语版 (Rev.A): PDF
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TSSOP (DGG) 48 查看选项
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

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