FlatLink™ 变送器

SN75LVDS83 不推荐用于新设计
虽然我们会继续生产此产品供先前的设计使用,但不推荐在新设计中使用此产品。请考虑从这些替代产品中选择一款:
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功能与比较器件相似
SN75LVDS83B 正在供货 10MHz 至 135MHz、28 位 LVDS 变送器/串行器与 FlatLink™ 集成电路 SN75LVDS83B supports a wider PLL frequency range of 10-85MHz and the SN75LVDS83C supports a PLL frequency range of 10-135MHz.

产品详情

Protocols Catalog Rating Catalog Operating temperature range (°C) 0 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) 0 to 70
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • 4:28 Data Channel Compression at up to 238 MBytes/s Throughput
  • Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI
  • 28 Data Channels and Clock-In Low-Voltage TTL
  • 4 Data Channels and Clock-Out Low-Voltage Differential
  • Operates From a Single 3.3-V Supply With 250 mW (Typ)
  • ESD Protection Exceeds 6 kV
  • 5-V Tolerant Data Inputs
  • Selectable Rising or Falling Edge-Triggered Inputs
  • Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range . . . 31 MHz to 68 MHz
  • No External Components Required for PLL
  • Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Improved Replacement for the DS90C581

FlatLink is a registered trademark of Texas Instruments.

  • 4:28 Data Channel Compression at up to 238 MBytes/s Throughput
  • Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI
  • 28 Data Channels and Clock-In Low-Voltage TTL
  • 4 Data Channels and Clock-Out Low-Voltage Differential
  • Operates From a Single 3.3-V Supply With 250 mW (Typ)
  • ESD Protection Exceeds 6 kV
  • 5-V Tolerant Data Inputs
  • Selectable Rising or Falling Edge-Triggered Inputs
  • Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range . . . 31 MHz to 68 MHz
  • No External Components Required for PLL
  • Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Improved Replacement for the DS90C581

FlatLink is a registered trademark of Texas Instruments.

The SN75LVDS83 FlatLink transmitter contains four 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and five low-voltage differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit links with the SN75LVDS86 receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL) terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all internal registers to a low level.

The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0°C to 70°C.

The SN75LVDS83 FlatLink transmitter contains four 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and five low-voltage differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit links with the SN75LVDS86 receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL) terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all internal registers to a low level.

The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0°C to 70°C.

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技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 FlatLink (tm) Transmitters 数据表 (Rev. I) 2009年 5月 19日
应用手册 High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 2018年 11月 9日
应用手册 Flatlink Data Transmission System Design Overview (Rev. A) 2001年 6月 1日
应用手册 Time Budgeting of the Flatlink Interface Application Report 1997年 6月 11日

设计和开发

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仿真模型

SN75LVDS83 IBIS Model

SLLC105.ZIP (5 KB) - IBIS Model
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用户指南: PDF
英语版 (Rev.A): PDF
封装 引脚 下载
TSSOP (DGG) 56 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

支持和培训

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