SN74LVC2G125-Q1 汽车类具有三态输出的双路总线缓冲器闸 | 德州仪器 TI.com.cn

SN74LVC2G125-Q1
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汽车类具有三态输出的双路总线缓冲器闸

汽车类具有三态输出的双路总线缓冲器闸 - SN74LVC2G125-Q1
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描述

The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性

  • Qualified for Automotive Applications
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

参数

与其它产品相比 同向缓冲器/驱动器 邮件 下载到电子表格中
Part number 立即下单 Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) IOL (Max) (mA) IOH (Max) (mA) ICC (uA) Input type Output type Features Data rate (Mbps) Rating Package Group
SN74LVC2G125-Q1 立即下单 LVC     1.65     5.5     2     32     -32     10     Standard CMOS     3-State     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
300     Automotive     SM8 | 8
VSSOP | 8    
SN74LVC2G125 立即下单 LVC     1.65     5.5     2     32     -32     10     Standard CMOS     3-State     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
300     Catalog     DSBGA | 8
SM8 | 8
VSSOP | 8