The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Part number | 立即下单 | Technology Family | VCC (Min) (V) | VCC (Max) (V) | Channels (#) | IOL (Max) (mA) | IOH (Max) (mA) | ICC (uA) | Input type | Output type | Features | Data rate (Mbps) | Rating | Package Group |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SN74LVC2G125-Q1 |
|
LVC | 1.65 | 5.5 | 2 | 32 | -32 | 10 | Standard CMOS | 3-State |
Balanced outputs
Very high speed (tpd 5-10ns) Partial power down (Ioff) Over-voltage tolerant inputs |
300 | Automotive |
SM8 | 8
VSSOP | 8 |
SN74LVC2G125 |
|
LVC | 1.65 | 5.5 | 2 | 32 | -32 | 10 | Standard CMOS | 3-State |
Balanced outputs
Very high speed (tpd 5-10ns) Partial power down (Ioff) Over-voltage tolerant inputs |
300 | Catalog |
DSBGA | 8
SM8 | 8 VSSOP | 8 |