SCES885 April 2017 SN74LVC1G80-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TA = -40°C to +85°C
    7. 6.7 Timing Requirements: TA = -40°C to +125°C
    8. 6.8 Switching Characteristics: TA = -40°C to +85°C, CL = 15 pF
    9. 6.9 Switching Characteristics: TA = -40°C to +85°C, CL = 30 pF or 50 pF
    10. 6.10Switching Characteristics: TA = -40°C to +125°C, CL = 30 pF or 50 pF
    11. 6.11Operating Characteristics
    12. 6.12Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Balanced High-Drive CMOS Push-Pull Outputs
      2. 8.3.2Standard CMOS Inputs
      3. 8.3.3Clamp Diodes
      4. 8.3.4Partial Power Down (Ioff)
      5. 8.3.5Over-Voltage Tolerant Inputs
    4. 8.4Device Functional Modes
  9. Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
      3. 9.2.3Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Documentation Support
      1. 12.1.1Related Documentation
    2. 12.2Receiving Notification of Documentation Updates
    3. 12.3Community Resources
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
    • ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Maximum tpd of 6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff supports Partial-Power-Down Mode and Back-Drive Protection

Applications

  • Automotive Infotainment
  • Automotive Cluster
  • Automotive ADAS
  • Automotive Body Electronics
  • Automotive HEV/EV Powertrain

Description

The SN74LVC1G80-Q1 device is an automotive AEC-Q100 qualified, single positive-edge-triggered D-type flip-flop that is designed for 1.65-V to 5.5-V VCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE
SN74LVC1G80-Q1SC70 (5)2.00 mm × 1.25 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN74LVC1G80-Q1 LD_CES221.gif
TG - Transmission Gate