SN74LV32A-EP

Name: SN74LV32A-EP
Brand: TI
SKU: SN74LV32A-EP
Price: 0.649 USD

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4 通道、双输入、2V 至 5.5V、高速 (7ns) 或门（增强型产品）

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数据表

document-pdfAcrobat SN74LV32A-EP 数据表 (Rev. B) (英语)

SN74LV32A-EP

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数据表

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产品详情

Technology family

LV-A

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Number of channels

4

Inputs per channel

2

IOL (max) (mA)

50

IOH (max) (mA)

-50

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

70

Rating

HiRel Enhanced Product

Operating temperature range (°C)

-55 to 125

Technology family

LV-A

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Number of channels

4

Inputs per channel

2

IOL (max) (mA)

50

IOH (max) (mA)

-50

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

70

Rating

HiRel Enhanced Product

Operating temperature range (°C)

-55 to 125

TSSOP (PW)

14

32 mm² 5 x 6.4

Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Extended Temperature Performance of -55°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree⁽¹⁾
2-V to 5.5-V V_CC Operation
Max t_pd of 7.5 ns at 5 V
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) > 2.3 V at V_CC = 3.3 V, T_A = 25°C
Supports Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power-Down Mode Operation

⁽¹⁾Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified
performance and environmental limits.

Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Extended Temperature Performance of -55°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree⁽¹⁾
2-V to 5.5-V V_CC Operation
Max t_pd of 7.5 ns at 5 V
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) > 2.3 V at V_CC = 3.3 V, T_A = 25°C
Supports Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power-Down Mode Operation

⁽¹⁾Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified
performance and environmental limits.

This quadruple 2-input positive-OR gate is designed for 2-V to 5.5-V V_CC operation.

The SN74LV32A-EP performs the Boolean function Y = A + B or Y = (A\ • B\)\ in positive logic.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This quadruple 2-input positive-OR gate is designed for 2-V to 5.5-V V_CC operation.

The SN74LV32A-EP performs the Boolean function Y = A + B or Y = (A\ • B\)\ in positive logic.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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