可提供此产品的更新版本

open-in-new 比较替代产品
功能优于比较器件,可直接替换
SN74AXCH1T45 正在供货 单位双电源总线收发器 Pin-to-pin upgrade with a wider voltage range and improved performance

产品详情

Technology family AVC Applications GPIO Bits (#) 1 High input voltage (min) (V) 1 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 20 Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Applications GPIO Bits (#) 1 High input voltage (min) (V) 1 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 20 Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 6 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1
  • Available in the Texas Instruments NanoStar&trade
    and NanoFree™ Packages
  • Control Inputs (DIR) VIH and VIL Levels Are
    Referenced to VCCA Voltage
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup and Pulldown Resistors
  • VCC Isolation
  • Fully Configurable Dual-Rail Design
  • I/Os Are 4.6-V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • Typical Max Data Rates
    • 500 Mbps (1.8-V to 3.3-V Translation)
    • 320 Mbps (<1.8-V to 3.3-V Translation)
    • 320 Mbps (Translate to 2.5 V or 1.8 V)
    • 280 Mbps (Translate to 1.5 V)
    • 240 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • Human-Body Model (A114-A): 2000 V
    • Machine Model (A115-A): 200 V
    • Charged-Device Model (C101): 1000 V
  • Available in the Texas Instruments NanoStar&trade
    and NanoFree™ Packages
  • Control Inputs (DIR) VIH and VIL Levels Are
    Referenced to VCCA Voltage
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup and Pulldown Resistors
  • VCC Isolation
  • Fully Configurable Dual-Rail Design
  • I/Os Are 4.6-V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • Typical Max Data Rates
    • 500 Mbps (1.8-V to 3.3-V Translation)
    • 320 Mbps (<1.8-V to 3.3-V Translation)
    • 320 Mbps (Translate to 2.5 V or 1.8 V)
    • 280 Mbps (Translate to 1.5 V)
    • 240 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • Human-Body Model (A114-A): 2000 V
    • Machine Model (A115-A): 200 V
    • Charged-Device Model (C101): 1000 V

The SN74AVCH1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH1T45 is designed for asynchronous communication between two data buses. The device transmits data from either the A bus to the B bus, or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input.

The SN74AVCH1T45 is designed so that the DIR input is referenced to VCCA.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device.

The VCC isolation feature ensures that if either VCCA or VCCB is at GND, then the outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74AVCH1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH1T45 is designed for asynchronous communication between two data buses. The device transmits data from either the A bus to the B bus, or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input.

The SN74AVCH1T45 is designed so that the DIR input is referenced to VCCA.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device.

The VCC isolation feature ensures that if either VCCA or VCCB is at GND, then the outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

下载 观看带字幕的视频 视频

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 15
类型 标题 下载最新的英语版本 日期
* 数据表 SN74AVCH1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs 数据表 (Rev. E) PDF | HTML 2016年 3月 16日
选择指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
应用手册 Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 选择正确的电平转换解决方案 (Rev. A) 英语版 (Rev.A) 2006年 3月 23日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
更多文献资料 LCD Module Interface Application Clip 2003年 5月 9日
用户指南 AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
更多文献资料 Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
应用手册 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
应用手册 Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
应用手册 AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

评估板

5-8-LOGIC-EVM — 支持 5 至 8 引脚 DCK、DCT、DCU、DRL 和 DBV 封装的通用逻辑评估模块

灵活的 EVM 设计用于支持具有 5 至 8 引脚数且采用 DCK、DCT、DCU、DRL 或 DBV 封装的任何器件。
用户指南: PDF
TI.com 上无现货
评估板

AVCLVCDIRCNTRL-EVM — 适用于方向控制双向转换器件、支持 AVC 和 LVC 的通用 EVM

该通用 EVM 旨在支持 1、2、4 和 8 通道 LVC 和 AVC 方向控制转换器件。它还以相同数量的通道支持总线保持和汽车 Q1 器件。AVC 是低电压转换器件,具有 12mA 的较低驱动强度。LVC 是 1.65 至 5.5V 的较高电压转换器件,具有 32mA 的较高驱动强度。

用户指南: PDF | HTML
英语版 (Rev.B): PDF | HTML
TI.com 上无现货
仿真模型

SN74AVCH1T45 IBIS Model (Rev. A)

SCEM438A.ZIP (118 KB) - IBIS Model
参考设计

TIDA-00352 — SDI 视频聚合参考设计

这款经过验证的参考设计是一个完整的四通道 SDI 聚合与解聚解决方案。使用一个 TLK10022 将四个同步 HD-SDI 源聚合到一条 5.94 Gbps 串行链路中。串行数据经由铜缆或光缆传输;使用另一个 TLK10022 来解聚并无缝重现原始视频内容。
测试报告: PDF
原理图: PDF
参考设计

TIDA-00309 — DisplayPort 视频 4:1 聚合参考设计

这款经过验证的参考设计是一个完整的四通道 DisplayPort 聚合与解聚解决方案。其中使用一个 TLK10022 将四个同步 DisplayPort (DP) 源一起聚合到一条 10.8 Gbps 串行链路中。串行数据经由铜缆或光缆传输,其中使用另一个 TLK10022 来解聚并无缝重现原始视频内容。
测试报告: PDF
原理图: PDF
封装 引脚 下载
DSBGA (YZP) 6 查看选项
SOT-23 (DBV) 6 查看选项
SOT-SC70 (DCK) 6 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

支持和培训

视频