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SN74ALVC244-EP

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具有总线保持和三态输出的 8 通道、1.65V 至 3.6V 缓冲器（增强型产品）

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SN74ALVC244-EP

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产品详情

Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 8 IOL (max) (mA) 24 Supply current (max) (µA) 24 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 85
Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 8 IOL (max) (mA) 24 Supply current (max) (µA) 24 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 85
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Operates From 1.65-V to 3.6-V VCC
  • Max tpd of 2.8 ns at 3.3-V VCC
  • ±24-mA Output Drive at 3.3-V VCC
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Operates From 1.65-V to 3.6-V VCC
  • Max tpd of 2.8 ns at 3.3-V VCC
  • ±24-mA Output Drive at 3.3-V VCC
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

This octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC244 is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC244 is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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类型 标题 下载最新的英语版本 日期
* 数据表 SN74ALVC244-EP 数据表 (Rev. A) 2004年 9月 29日
* VID SN74ALVC244-EP VID V6204762 2016年 6月 21日
* 辐射与可靠性报告 SN74ALVC244IPWREP Reliability Report 2012年 3月 15日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
用户指南 ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002年 8月 1日
更多文献资料 Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
应用手册 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
应用手册 Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
应用手册 TI SN74ALVC16835 Component Specification Analysis for PC100 1998年 8月 3日
应用手册 Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998年 5月 13日
应用手册 Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
应用手册 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
应用手册 CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
应用手册 Live Insertion 1996年 10月 1日
应用手册 Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

设计和开发

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TSSOP (PW) 20 查看选项
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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