SN74ACT2229
- Dual Independent FIFOs Organized as:
64 Words by 1 Bit Each - SN74ACT2227
256 Words by 1 Bit Each - SN74ACT2229 - Free-Running Read and Write Clocks Can Be Asynchronous or Coincident on Each FIFO
- Input-Ready Flags Synchronized to Write Clocks
- Output-Ready Flags Synchronized to Read Clocks
- Half-Full and Almost-Full/Almost-Empty Flags
- Support Clock Frequencies up to 60 MHz
- Access Times of 9 ns
- 3-State Data Outputs
- Low-Power Advanced CMOS Technology
- Packaged in 28-Pin SOIC Package
The SN74ACT2227 and SN74ACT2229 are dual FIFOs suited for a wide range of serial-data buffering applications including elastic stores for frequencies up to OC-1 telecommunication rates. Each FIFO on the chip is arranged as 64 × 1 (SN74ACT2227) or 256 × 1 (SN74ACT2229) and has control signals and status flags for independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR), half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).
Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high. Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read and write clocks of a FIFO can be asynchronous to one another. A FIFO data output (1Q or 2Q) is in the high-impedance state when its output-enable (1OE or 2OE) input is low.
Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or 2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock (1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written and read asynchronously.
A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data output is not stored in the FIFO.
The SN74ACT2227 and SN74ACT2229 are characterized for operation from -40°C to 85°C.
For more information on this device family, see the application report FIFOs With a Word Width of One Bit (literature number SCAA006).
技术文档
| 类型 | 标题 | 下载最新的英语版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 数据表 | Dual 64 X 1, Dual 256 X 1 First-In First-Out Memories 数据表 (Rev. C) | 1997年 10月 1日 | |||
| 应用手册 | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021年 7月 26日 | ||||
| 选择指南 | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||||
| 应用手册 | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||||
| 选择指南 | 逻辑器件指南 2014 (Rev. AA) | 最新英语版本 (Rev.AB) | 2014年 11月 17日 | |||
| 用户指南 | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||||
| 应用手册 | 选择正确的电平转换解决方案 (Rev. A) | 英语版 (Rev.A) | 2006年 3月 23日 | |||
| 应用手册 | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||||
| 应用手册 | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||||
| 应用手册 | CMOS Power Consumption and CPD Calculation (Rev. B) | 1997年 6月 1日 | ||||
| 应用手册 | 使用逻辑器件进行设计 (Rev. C) | 1997年 6月 1日 | ||||
| 应用手册 | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 1996年 4月 1日 | ||||
| 应用手册 | FIFOs With A Word Width Of One Bit (Rev. A) | 1996年 3月 1日 | ||||
| 应用手册 | Power-Dissipation Calculations for TI FIFO Products (Rev. A) | 1996年 3月 1日 |
设计和开发
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