SN65LVDT388A 八路 LVDS 接收器 | 德州仪器 TI.com.cn

SN65LVDT388A (正在供货)

八路 LVDS 接收器

八路 LVDS 接收器 - SN65LVDT388A
数据表
 

描述

This family of 4-, 8-, or 16-differential line receivers (with optional integrated termination) implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail.

Any of the differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this external resistor by integrating it with the receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, the 8- or 16-channel driver (the SN65LVDS389 or SN65LVDS387, respectively), over 200 million data transfers per second in single-edge clocked systems are possible with little power.

The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

特性

  • Four- (’390), Eight- (’388A), or Sixteen- (’386)
    Line Receivers Meet or Exceed the Requirements
    of ANSI TIA/EIA-644 Standard
  • Integrated 110-Ω Line Termination
    Resistors on LVDT Products
  • Designed for Signaling Rates Up to 250 Mbps
  • SN65 Versions Bus-Terminal ESD Exceeds
    15 kV
  • Operates From a Single 3.3-V Supply
  • Typical Propagation Delay Time of 2.6 ns
  • Output Skew 100 ps (Typical) Part-To-Part
    Skew Is Less Than 1 ns
  • LVTTL Levels Are 5-V Tolerant
  • Open-Circuit Fail Safe
  • Flow-Through Pinout
  • Packaged in Thin Shrink Small-Outline
    Package With 20-mil Terminal Pitch

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参数 与其它产品相比 缓冲器、驱动器/接收器和交叉点

 
Device type
Protocols
Number of Tx
Number of Rx
Input signal
Output signal
Signaling Rate (Mbps)
ESD HBM (kV)
Function
Operating temperature range (C)
Package Group
Package size: mm2:W x L (PKG)
SN65LVDT388A SN65LVDS386 SN65LVDS387 SN65LVDS388A SN65LVDS389 SN75LVDS388A SN75LVDT388A
Receiver     Receiver     Driver     Receiver     Driver     Receiver     Receiver    
LVDS     LVDS     LVDS     LVDS     LVDS     LVDS     LVDS    
0     0     16     0     8     0     0    
8     16     0     8     0     8     8    
LVDS     LVDS     LVTTL     LVDS     LVTTL     LVDS     LVDS    
LVTTL     LVTTL     LVDS     LVTTL     LVDS     LVTTL     LVTTL    
200     250     630     200     630     250     250    
15     15     15     15     15     4     4    
Receiver     Receiver     Driver     Receiver     Driver     Receiver     Receiver    
-40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     0 to 70     0 to 70    
TSSOP | 38     TSSOP | 64     TSSOP | 64     TSSOP | 38     TSSOP | 38     TSSOP | 38     TSSOP | 38    
38TSSOP: 62 mm2: 6.4 x 9.7 (TSSOP | 38)     64TSSOP: 138 mm2: 8.1 x 17 (TSSOP | 64)     64TSSOP: 138 mm2: 8.1 x 17 (TSSOP | 64)     38TSSOP: 62 mm2: 6.4 x 9.7 (TSSOP | 38)     38TSSOP: 62 mm2: 6.4 x 9.7 (TSSOP | 38)     38TSSOP: 62 mm2: 6.4 x 9.7 (TSSOP | 38)     38TSSOP: 62 mm2: 6.4 x 9.7 (TSSOP | 38)