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SN65LVDS94

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Serdes 解串器

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SN65LVDS94

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产品详情

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • 4:28 Data Channel Expansion at up to 1.904 Gigabits per Second Throughput
  • Suited for Point-to-Point Subsystem Communication With Very Low EMI
  • 4 Data Channels and Clock Low-Voltage Differential Channels in and 28 Data and Clock Out Low-Voltage TTL Channels Out
  • Operates From a Single 3.3-V Supply and 250 mW (Typ)
  • 5-V Tolerant SHTDN\ Input
  • Rising Clock Edge Triggered Outputs
  • Bus Pins Tolerate 4-kV HBM ESD
  • Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
  • Consumes <1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range
      20 MHz to 65 MHz
  • No External Components Required for PLL
  • Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard
  • Industrial Temperature Qualified TA = -40°C to 85°C
  • Replacement for the DS90CR286
  • 4:28 Data Channel Expansion at up to 1.904 Gigabits per Second Throughput
  • Suited for Point-to-Point Subsystem Communication With Very Low EMI
  • 4 Data Channels and Clock Low-Voltage Differential Channels in and 28 Data and Clock Out Low-Voltage TTL Channels Out
  • Operates From a Single 3.3-V Supply and 250 mW (Typ)
  • 5-V Tolerant SHTDN\ Input
  • Rising Clock Edge Triggered Outputs
  • Bus Pins Tolerate 4-kV HBM ESD
  • Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
  • Consumes <1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range
      20 MHz to 65 MHz
  • No External Components Required for PLL
  • Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard
  • Industrial Temperature Qualified TA = -40°C to 85°C
  • Replacement for the DS90CR286

The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).

The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN\) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The SN65LVDS94 is characterized for operation over ambient air temperatures of -40°C to 85°C.

The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).

The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN\) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The SN65LVDS94 is characterized for operation over ambient air temperatures of -40°C to 85°C.
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类型 标题 下载最新的英语版本 日期
* 数据表 LVDS Serdes Receiver 数据表 (Rev. F) 2006年 1月 27日
应用手册 High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 2018年 11月 9日
应用简报 LVDS Serdes 48 EVM Kit Setup And Usage 1998年 12月 17日

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仿真模型

SN65LVDS94 IBIS Model

SLLC286.ZIP (6 KB) - IBIS Model
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用户指南: PDF
英语版 (Rev.A): PDF
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TSSOP (DGG) 56 查看选项
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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