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SN65LVDM1677

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16 通道 LVDM 收发器

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数据表

SN65LVDM1677

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产品详情

Function Transceiver Protocols LVDM, LVDS Number of transmitters 16 Number of receivers 16 Supply voltage (V) 3.3 Signaling rate (MBits) 200 Input signal LVDM, LVTTL Output signal LVDM, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols LVDM, LVDS Number of transmitters 16 Number of receivers 16 Supply voltage (V) 3.3 Signaling rate (MBits) 200 Input signal LVDM, LVTTL Output signal LVDM, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 64 137.7 mm² 17 x 8.1
  • Sixteen Low-Voltage Differential Transceivers. Designed for Signaling Rates up to 200 Mbps per Receiver or 650 Mbps per Transmitter.
  • Simplex (Point-to-Point) or Half-Duplex (Multipoint) Interface
  • Typical Differential Output Voltage of 340 mV Into a 50- Line Termination on 'LVDM1677 Product
  • Propagation Delay Time:
    • Driver: 2.5 ns Typ
    • Receiver: 3 ns Typ
  • Driver is High Impedance When Disabled or With VCC < 1.5 V for Power Up/Down Glitch-Free Performance and Hot-Plugging Events
  • Bus-Terminal ESD Protection Exceeds 12 kV
  • Low-Voltage TTL (LVTTL) Logic Input Levels Are 5-V Tolerant
  • Packaged in Thin Shrink Small-Outline Package With 20 mil Terminal Pitch
  • Sixteen Low-Voltage Differential Transceivers. Designed for Signaling Rates up to 200 Mbps per Receiver or 650 Mbps per Transmitter.
  • Simplex (Point-to-Point) or Half-Duplex (Multipoint) Interface
  • Typical Differential Output Voltage of 340 mV Into a 50- Line Termination on 'LVDM1677 Product
  • Propagation Delay Time:
    • Driver: 2.5 ns Typ
    • Receiver: 3 ns Typ
  • Driver is High Impedance When Disabled or With VCC < 1.5 V for Power Up/Down Glitch-Free Performance and Hot-Plugging Events
  • Bus-Terminal ESD Protection Exceeds 12 kV
  • Low-Voltage TTL (LVTTL) Logic Input Levels Are 5-V Tolerant
  • Packaged in Thin Shrink Small-Outline Package With 20 mil Terminal Pitch

The SN65LVDM1676 and SN65LVDM1677 (integrated termination) are sixteen differential line transmitters or receivers (tranceivers) that use low-voltage differential signaling (LVDS) to achieve signaling rates up to 200 Mbps per transceiver configured as a receiver and up to 650 Mbps per transceiver configured as a transmitter. These products are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers are doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50- load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of 100 mV with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of transceivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

The SN65LVDM1676 and SN65LVDM1677 are characterized for operation from -40°C to 85°C.

The SN65LVDM1676 and SN65LVDM1677 (integrated termination) are sixteen differential line transmitters or receivers (tranceivers) that use low-voltage differential signaling (LVDS) to achieve signaling rates up to 200 Mbps per transceiver configured as a receiver and up to 650 Mbps per transceiver configured as a transmitter. These products are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers are doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50- load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of 100 mV with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of transceivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

The SN65LVDM1676 and SN65LVDM1677 are characterized for operation from -40°C to 85°C.
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类型 标题 下载最新的英语版本 日期
* 数据表 High-Speed Differential Line Transceivers 数据表 (Rev. D) 2007年 6月 14日
应用手册 AN-1926：M-LVDS 简介及其时钟和数据分配应用 (Rev. C) PDF | HTML 英语版 (Rev.C) PDF | HTML 2023年 7月 5日
应用简报 How Far, How Fast Can You Operate MLVDS? 2018年 8月 6日
应用手册 SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) 2001年 11月 20日

设计和开发

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仿真模型

SN65LVDM1676/77 IBIS Model Version 1.1 (Rev. A)

SLLC051A.ZIP (38 KB) - IBIS Model
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 制造厂地点
  • 封装厂地点

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