SLLS934F November   2008  – November 2015 SN65HVD11-HT

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Driver Electrical Characteristics
    6. 6.6 Receiver Electrical Characteristics
    7. 6.7 Driver Switching Characteristics
    8. 6.8 Receiver Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Standby Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.3 6 V
Voltage at A or B –9 14 V
Input voltage at D, DE, R, or RE –0.5 VCC + 0.5 V
Voltage input, transient pulse, A and B, through 100 Ω (see Figure 20) –50 50 V
IO Receiver output current –11 11 mA
Continuous total power dissipation See Thermal Information
(1) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) A, B, and GND ±16000 V
All pins ±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 3 3.6 V
VI or VIC Voltage at any bus terminal (separately or common-mode) –7(1) 12 V
VIH High-level input voltage D, DE, RE 2 VCC V
VIL Low-level input voltage D, DE, RE 0 0.8 V
VID Differential input voltage Figure 16 –12 12 V
IOH High-level output current Driver –60 mA
Receiver –8
IOL Low-level output current Driver 60 mA
Receiver 8
RL Differential load resistance 54 60 Ω
CL Differential load capacitance 50 pF
Signaling rate 10 Mbps
TJ(2) Operating junction temperature TA = –55°C to 125°C 129 °C
TA = 175°C 179
TA = 210°C 214
(1) The algebraic convention, in which the least-positive (most-negative) limit is designated as minimum, is used in this data sheet.
(2) See Thermal Information table for information regarding this specification.

6.4 Thermal Information

THERMAL METRIC(1) SN65HVD11-HT UNIT
D (SOIC) JD (CDIP SB) HKJ (CFP) HKQ (CFP)
8 PINS 8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 101.5 73.9 N/A 170 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.6 N/A N/A 6.2 °C/W
RθJB Junction-to-board thermal resistance 45.1 39.8 N/A 195 °C/W
ψJT Junction-to-top characterization parameter 4.8 6.9 N/A 3.8 °C/W
ψJB Junction-to-board characterization parameter 41.8 49.2 N/A 146.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 9.1 6.2 N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Driver Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
|VOD| Differential output voltage IO = 0 2 VCC V
RL = 54 Ω, See Figure 10 1
Vtest = –7 V to 12 V,
See Figure 11		 1
Δ|VOD| Change in magnitude of differential output voltage Vtest = –7 V to 12 V,
See Figure 10 and Figure 11		 –0.2 0.2 V
VOC(PP) Peak-to-peak common mode output voltage See Figure 12 400 mV
VOC(SS) Steady-state common mode output voltage See Figure 12 1.4 2.5 V
ΔVOC(SS) Change in steady-state common mode output voltage See Figure 12 –0.06 0.06 V
IOZ High-impedance output current See receiver input currents
II Input current D TA = –55°C to 125°C –100 0 μA
TA = 175°C(1) –100 3
TA = 210°C(2) –100 3
DE 0 100
IOS Short circuit output current –7 V ≤ VO ≤ 12 V –250 250 mA
C(OD) Differential output capacitance VOD = 0.4 sin (4E6πt) + 0.5 V,
DE = 0 V		 18 pF
ICC Supply current RE = VCC,
D and
DE = VCC,
No load		 Receiver disabled and driver enabled TA = –55°C to 125°C 11 15.5 mA
TA = 175°C(1) 11.5 17.5
TA = 210°C(2) 14 18
RE = VCC,
D = VCC,
DE = 0 V,
No load		 Receiver disabled and driver disabled (standby) TA = –55°C to 125°C 2.5 20 μA
TA = 175°C(1) 20 150
TA = 210°C(2) 175 450
RE = 0 V,
D and
DE = VCC,
No load		 Receiver enabled and driver enabled TA = –55°C to 125°C 11 15.5 mA
TA = 175°C(1) 11 17.5
TA = 210°C(2) 11 18
(1) Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
(2) Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.

6.6 Receiver Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage IO = –8 mA –0.01 V
VIT– Negative-going input threshold voltage IO = 8 mA –0.2 V
Vhys Hysteresis voltage
(VIT+ –VIT–)		 TA = –55°C to 125°C 35 mV
TA = 175°C(1) 41
TA = 210°C(2) 41
VIK Enable-input clamp voltage II = –18 mA –1.5 V
VOH High-level output voltage VID = 200 mV, IOH = –8 mA,
See Figure 16		 2.4 V
VOL Low-level output voltage VID = –200 mV, IOL = 8 mA,
See Figure 16		 0.4 V
IOZ High-impedance state output current VO = 0 or VCC,RE = VCC –1 1 μA
II Bus input current VA or VB = 12 V Other input
at 0 V		 TA = –55°C to 125°C 0.075 0.11 mA
TA = 175°C(1) 0.1 0.15
TA = 210°C(2) 0.1 0.15
VA or VB = 12 V,
VCC = 0 V		 TA = –55°C to 125°C 0.085 0.13
TA = 175°C(1) 0.12 0.16
TA = 210°C(2) 0.12 0.16
VA or VB = –7 V TA = –55°C to 125°C –0.1 –0.05
TA = 175°C(1) –0.3 –0.15
TA = 210°C(2) –0.3 –0.15
VA or VB = –7 V,
VCC = 0 V		 TA = –55°C to 125°C –0.1 –0.05
TA = 175°C(1) –0.3 –0.15
TA = 210°C(2) –0.3 –0.15
IIH High-level input current, RE VIH = 2 V TA = –55°C to 125°C –30 0 μA
TA = 175°C(1) –30 3
TA = 210°C(2) –30 3
IIL Low-level input current, RE VIL = 0.8 V –30 0 μA
CID Differential input capacitance VID = 0.4 sin (4E6πt) + 0.5 V,
DE at 0 V		 TA = –55°C to 125°C 15 pF
TA = 175°C(1) 18
TA = 210°C(2) 18
ICC Supply current RE = 0 V,
D and DE = 0 V,
No load		 Receiver enabled and driver disabled TA = –55°C to 125°C 5 8 mA
TA = 175°C(1) 7.5 8.5
TA = 210°C(2) 7.5 10
RE = VCC,
D = VCC,
DE = 0 V,
No load		 Receiver disabled and driver disabled (standby) TA = –55°C to 125°C 2.5 20 μA
TA = 175°C(1) 12.5 200
TA = 210°C(2) 175 450
RE = 0 V,
D and DE = VCC,
No load		 Receiver enabled and driver enabled TA = –55°C to 125°C 11 15.5 mA
TA = 175°C(1) 11.5 17.5
TA = 210°C(2) 14 18
(1) Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
(2) Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.

6.7 Driver Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output RL = 54 Ω,
CL = 50 pF,
See Figure 13		 18 25 40 ns
tPHL Propagation delay time, high-to-low-level output 18 25 40 ns
tr Differential output signal rise time TA = –55°C to 125°C 10 21 30 ns
TA = 175°C(1) 10 22 30
TA = 210°C(2) 10 22 30
tf Differential output signal fall time TA = –55°C to 125°C 10 21 30 ns
TA = 175°C(1) 10 22 30
TA = 210°C(2) 10 22 30
tsk(p) Pulse skew (|tPHL – tPLH|) 2.5 ns
tsk(pp)(3) Part-to-part skew (tPHL or tPLH) 11 ns
tPZH Propagation delay time, high-impedance to high-level output RL = 110 Ω,
RE = 0 V,
See Figure 14		 55 ns
tPHZ Propagation delay time, high-level to high-impedance output 55 ns
tPZL Propagation delay time, high-impedance to low-level output RL = 110 Ω,
RE = 0 V,
See Figure 15		 55 ns
tPLZ Propagation delay time, low-level to high-impedance output 75 ns
tPZH Propagation delay time, standby to high-level output RL = 110 Ω,
RE = 3 V,
See Figure 14		 6 μs
tPZL Propagation delay time, standby to low-level output RL = 110 Ω,
RE = 3 V,
See Figure 15		 6 μs
(1) Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
(2) Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

6.8 Receiver Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output VID = –1.5 V to 1.5 V,
CL = 15 pF,
See Figure 17		 30 55 70 ns
tPHL Propagation delay time, high-to-low-level output 30 55 70 ns
tsk(p) Pulse skew (|tPHL – tPLH|) 4 ns
tsk(pp)(3) Part-to-part skew 15 ns
tr Output signal rise time CL = 15 pF,
See Figure 17		 TA = –55°C to 125°C 1 3 5 ns
TA = 175°C(1) 1 4 5
TA = 210°C(2) 1 4 5
tf Output signal fall time TA = –55°C to 125°C 1 3 5 ns
TA = 175°C(1) 1 4 5
TA = 210°C(2) 1 4 5
tPZH(2) Output enable time to high level CL = 15 pF, DE = 3 V,
See Figure 18		 15 ns
tPZL(2) Output enable time to low level 15 ns
tPHZ Output disable time from high level 20 ns
tPLZ Output disable time from low level 15 ns
tPZH(3) Propagation delay time, standby-to-high-level output CL = 15 pF, DE = 0,
See Figure 19		 6 μs
tPZL(3) Propagation delay time, standby-to-low-level output 6 μs
(1) Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
(2) Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

xxx

SN65HVD11-HT op_life2_slls934.gif
1. See data sheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
3. The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
4. Wirebond fail mode applicable for D package only.
5. Wirebond life approaches 0 hours < 200°C which is only true of the HD device.
Figure 1. SN65HVD11SJD/SKGDA/SHKJ/SHKQ/HD
Operating Life Derating Chart
SN65HVD11-HT de_vod_time_lls505.gif

NOTE:

The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
Figure 2. Driver Enable Time From De to VOD

6.9 Typical Characteristics

SN65HVD11-HT tc_sup-cur2_lls505.gif
Figure 3. RMS Supply Current vs Signaling Rate
SN65HVD11-HT tc_hilev_lls505.gif
Figure 5. High-Level Output Current vs Driver High-Level Output Voltage
SN65HVD11-HT tc_drdiff1_lls934.gif
Figure 7. Driver Differential Output vs Free-Air Temperature
SN65HVD11-HT en_v_cmv_lls505.gif
Figure 9. Enable Time vs Common Mode Voltage  (See Figure 2)
SN65HVD11-HT tc_busin2_lls505.gif
Figure 4. Bus Input Current vs Bus Input Voltage
SN65HVD11-HT tc_lowlev_lls505.gif
Figure 6. Low-Level Output Current vs Driver Low-Level Output Voltage
SN65HVD11-HT tc_droutp_lls505.gif
Figure 8. Driver Output Current vs Supply Voltage