产品详情

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type TTL Output type TTL Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs Technology family ALS Rating Military Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type TTL Output type TTL Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs Technology family ALS Rating Military Operating temperature range (°C) -55 to 125
LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Two-Way Asynchronous Communication Between Data Buses
  • pnp Inputs Reduce dc Loading
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

  • Two-Way Asynchronous Communication Between Data Buses
  • pnp Inputs Reduce dc Loading
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

These quadruple bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing. These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the output-enable (OEBA and ) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.

The dual-enable configuration gives the quadruple bus transceivers the capability to store data by simultaneously enabling OEBA and . Each output reinforces its input in this transceiver configuration. When both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (eight in all) retain their states. The 4-bit codes appearing on the two sets of buses are identical.

The SN54ALS243A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS243A is characterized for operation from 0°C to 70°C.

 

 

These quadruple bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing. These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the output-enable (OEBA and ) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.

The dual-enable configuration gives the quadruple bus transceivers the capability to store data by simultaneously enabling OEBA and . Each output reinforces its input in this transceiver configuration. When both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (eight in all) retain their states. The 4-bit codes appearing on the two sets of buses are identical.

The SN54ALS243A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS243A is characterized for operation from 0°C to 70°C.

 

 

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类型 标题 下载最新的英语版本 日期
* 数据表 Quadruple Bus Transceivers With 3-State Outputs 数据表 (Rev. B) 1994年 12月 1日
* SMD SN54ALS243A SMD 84013022A 2016年 6月 21日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
应用手册 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
应用手册 使用逻辑器件进行设计 (Rev. C) 1997年 6月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
应用手册 Live Insertion 1996年 10月 1日
应用手册 Advanced Schottky (ALS and AS) Logic Families 1995年 8月 1日

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