SPNS155I September 2009  – June 2015 SM470R1B1M-HT

PRODUCTION DATA. 

  1. Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. Revision History
  3. Device Characteristics
  4. Bare Die
    1. 4.1Bare Die Information
  5. Pin Configuration and Functions
    1. 5.1Features
    2. 5.2Pin Functions (HFQ/HKP Package)
    3. 5.3Pin Functions (PGE Package)
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Thermal Characteristics
    6. 6.6  ZPLL and Clock Specifications
    7. 6.7  RST and PORRST Timings
    8. 6.8 JTAG Scan Interface Timing
    9. 6.9  Output Timings
    10. 6.10 Input Timings
    11. 6.11 Flash Timings
    12. 6.12 SPIn Master Mode Timing Parameters
    13. 6.13 SPIn Slave Mode Timing Parameters
    14. 6.14 SCIN Isosynchronous Mode Timings - Internal Clock
    15. 6.15 SCIN Isosynchronous Mode Timings - External Clock
    16. 6.16 I2C Timing
    17. 6.17 Standard Can Controller (SCC) Mode Timings
    18. 6.18 Expansion Bus Module Timing
    19. 6.19 Multi-Buffered A-to-D Converter (MibADC)
  7. Parameter Measurement Information
    1. 7.1 External Reference Resonator/Crystal Oscillator Clock Option
  8. Detailed Description
    1. 8.1Overview
      1. 8.1.1 MibADC
        1. 8.1.1.1 MibADC Event Trigger Enhancements
      2. 8.1.2 JTAG Interface
      3. 8.1.3 High-End Timer (HET) Timings
        1. 8.1.3.1 Minimum PWM Output Pulse Width
        2. 8.1.3.2 Minimum Input Pulses that can be Captured
      4. 8.1.4 Interrupt Priority (IEM to CIM)
      5. 8.1.5 Expansion Bus Module (EBM)
    2. 8.2Memory
      1. 8.2.1 Memory Selects
        1. 8.2.1.1 JTAG Security Module
        2. 8.2.1.2Memory Security Module
        3. 8.2.1.3RAM
        4. 8.2.1.4F05 Flash
          1. 8.2.1.4.1 Flash Protection Keys
          2. 8.2.1.4.2 Flash Read
          3. 8.2.1.4.3 Flash Pipeline Mode
          4. 8.2.1.4.4 Flash Program and Erase
          5. 8.2.1.4.5HET RAM
          6. 8.2.1.4.6 Peripheral Selects and Base Addresses
          7. 8.2.1.4.7 Direct-Memory Access (DMA)
  9. Device and Documentation Support
    1. 9.1Device Support
      1. 9.1.1 Device Identification Code Register
      2. 9.1.2 Timing Parameter Symbology
    2. 9.2Development Support
    3. 9.3 Device Nomenclature
    4. 9.4Documentation Support
    5. 9.5Community Resources
    6. 9.6Trademarks
    7. 9.7Electrostatic Discharge Caution
    8. 9.8Glossary
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1Packaging Information

1 Device Overview

1.1 Features

  • High-Performance Static CMOS Technology
  • SM470R1x 16-/32-Bit RISC Core (ARM7TDMI™)
    • 60-MHz System Clock (Pipeline Mode)
    • Independent 16-/32-Bit Instruction Set
    • Open Architecture With Third-Party Support
    • Built-In Debug Module
  • Integrated Memory
    • 1MB Program Flash
      • Two Banks With 16 Contiguous Sectors
    • 64KB Static RAM (SRAM)
    • Memory Security Module (MSM)
    • JTAG Security Module
  • Operating Features
    • Low-Power Modes: STANDBY and HALT
    • Industrial Temperature Range
  • 470+ System Module
    • 32-Bit Address Space Decoding
    • Bus Supervision for Memory/Peripherals
    • Digital Watchdog (DWD) Timer
    • Analog Watchdog (AWD) Timer
    • Enhanced Real-Time Interrupt (RTI)
    • Interrupt Expansion Module (IEM)
    • System Integrity and Failure Detection
    • ICE Breaker
  • Direct Memory Access (DMA) Controller
    • 32 Control Packets and 16 Channels
  • Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler
    • Multiply-by-4 or -8 Internal ZPLL Option
    • ZPLL Bypass Mode
  • Twelve Communication Interfaces:
    • Two Serial Peripheral Interfaces (SPIs)
    • 255 Programmable Baud Rates
    • Three Serial Communication Interfaces (SCIs)
      • 224 Selectable Baud Rates
      • Asynchronous/Isosynchronous Modes
    • Two High-End CAN Controllers (HECC)
      • 32-Mailbox Capacity
      • Fully Compliant With CAN Protocol, Version 2.0B
    • Five Inter-Integrated Circuit (I2C) Modules
      • Multi-Master and Slave Interfaces
      • Up to 400 Kbps (Fast Mode)
      • 7- and 10-Bit Address Capability
  • High-End Timer Lite (HET)
    • 12 Programmable I/O Channels:
      • 12 High-Resolution Pins
    • High-Resolution Share Feature (XOR)
    • High-End Timer RAM
      • 64-Instruction Capacity
  • External Clock Prescale (ECP) Module
    • Programmable Low-Frequency External Clock (CLK)
  • 12-Channel, 10-Bit Multi-Buffered ADC (MibADC)
    • 64-Word FIFO Buffer
    • Single- or Continuous-Conversion Modes
    • 1.55-µs Minimum Sample and Conversion Time
    • Calibration Mode and Self-Test Features
  • Flexible Interrupt Handling
  • Expansion Bus Module (EBM)
    • Supports 8- and 16-Bit Expansion Bus Memory Interface Mappings
    • 42 I/O Expansion Bus Pins
  • 46 Dedicated General-Purpose I/O (GIO) Pins and 47 Additional Peripheral I/Os
  • Sixteen External Interrupts
  • On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1 (1) (JTAG) Test-Access Port
  • Available in KGD, HFQ, HKP, and PGE Packages
(1) The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device.

1.2 Applications

  • Supports Extreme Temperature Applications:
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in Extreme (–55°C to 220°C) Temperature Range (1)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability
    • Texas Instruments' high temperature products use highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures.
(1) Custom temperature ranges available

1.3 Description

The SM470R1B1M(1)

(1) Throughout the remainder of this document, the SM470R1B1M will be referred to as either the full device name or as B1M.
devices are members of the Texas Instruments SM470R1x family of general-purpose 16-/32-bit reduced instruction set computer (RISC) microcontrollers. The B1M microcontroller offers high performance using the high-speed ARM7TDMI 16-/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16-/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The SM470R1B1M uses the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte of a word is stored at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The B1M RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The B1M devices contain the following:

  • ARM7TDMI 16-/32-bit RISC CPU
  • SM470R1x system module (SYS) with 470+ enhancements
  • 1MB flash
  • 64KB SRAM
  • ZPLL clock module
  • DWD timer
  • AWD timer
  • Enhanced RTI module
  • IEM
  • MSM
  • JTAG security module
  • Two SPI modules
  • Three SCI modules
  • Two HECC
  • Five I2C modules
  • 10-bit MibADC, with 12 input channels
  • HET controlling 12 I/Os
  • ECP
  • EBM
  • Up to 93 I/O pins

The functions performed by the 470+ system module (SYS) include:

  • Address decoding
  • Memory protection
  • Memory and peripherals bus supervision
  • Reset and abort exception management
  • Prioritization for all internal interrupt sources
  • Device clock control
  • Parallel signature analysis (PSA)

The enhanced RTI module on the B1M has the option to be driven by the oscillator clock. The DWD is a 25-bit resettable decrementing counter that provides a system reset when the watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (SPNU189).

The B1M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.

The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz or 30 MHz, depending on the input voltage. When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz or 60 MHz, depending on the input voltage. For more detailed information on the flash, see Section 8.2.1.4.

The MSM and the JTAG security module prevent unauthorized access and visibility to on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code.

The B1M device has twelve communication interfaces: two SPIs, three SCIs, two HECCs, and five I2Cs. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The HECC uses a serial, multimaster communication protocol that efficiently supports distributed realtime control with robust communication rates of up to 1 Mbps. These CAN peripherals are ideal for applications operating in noisy and harsh environments (for example, industrial fields) that require reliable serial communication or multiplexed wiring. The I2C module is a multimaster communication module providing an interface between the B1M microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports both 100 Kbps and 400 Kbps speeds. For more detailed functional information on the SPI, SCI, and CAN peripherals, see the specific reference guides (SPNU195, SPNU196, and SPNU197). For more detailed functional information on the I2C, see the TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (SPNU223).

The HET is an advanced intelligent timer that provides sophisticated timing functions for realtime applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well-suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (SPNU199).

The B1M HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (SPNU199).

The B1M device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (SPNU206).

The ZPLL clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1 to 8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), realtime interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other B1M device modules. For more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide (SPNU212).

NOTE

ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference.

The EBM is a standalone module that supports the multiplexing of the GIO functions and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module (EBM) Reference Guide (SPNU222).

The B1M device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (SPNU202).

Table 1-1 Device Information(1)

PART NUMBERPACKAGETA
SM470R1B1M-HTKGD (0)–55°C to 220°C
CFP (TBAR) (84)
CFP (84)
LQFP (144)–55°C to 150°C
  1. For more information, see Section 10, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

SM470R1B1M-HT fbd_pns155.gif
The enhanced RTI module is the system module with two extra bits to disable the ZPLL while in STANDBY mode.