主页 微控制器 (MCU) 和处理器 数字信号处理器 (DSP)
主页
微控制器 (MCU) 和处理器
数字信号处理器 (DSP)

SM34020APCM40

不推荐用于新设计

SM34020APCM40

立即订购
数据表

SM34020APCM40

不推荐用于新设计
数据表 立即订购

产品详情

Rating Military Operating temperature range (°C) to
Rating Military Operating temperature range (°C) to
QFP (PCM) 144 973.44 mm² 31.2 x 31.2
  • Class B High-Reliability Processing
  • 1-µm CMOS Technology
  • Commercial Operating Temperature Range 0°C to 70°C
  • SM34020APCM40 100-ns Instruction Cycle Time
  • Fully Programmable 32-Bit General-Purpose Processor With 512-Megabyte Linear Address Range (Bit Addressable)
  • Second-Generation Graphics System Processor (GSP)
    • Object-Code Compatible With the SM34010
    • Enhanced Instruction Set
    • Optimized Graphics Instructions
    • Coprocessor Interface
  • Pixel Processing, XY Addressing, and Window Checking Built Into the Instruction Set
  • Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit Pixel Size With 16 Boolean and Six Arithmetic Pixel Processing Options (Raster Ops)
  • 512-Byte LRU On-Chip Instruction Cache (I-Cache)
  • Optimized DRAM/Video RAM (VRAM) Interface
    • Page Mode for Burst-Memory Operations
    • Dynamic Bus Sizing (16-Bit and 32-Bit Transfers)
    • Byte-Oriented CAS Strobes
  • Flexible Host Processor Interface
    • Supports Host Transfers
    • Direct Access to All of the SM34020APCM40 Address Space
    • Implicit Addressing
    • Prefetch for Enhanced Read Access
  • Programmable CRT Control
    • Composite Synchronization Mode
    • Separate Synchronization Mode
    • Synchronization to External Synchronization
  • Direct Support for Special Features of 1M VRAMs
    • Load Write Mask
    • Load Color Mask
    • Block Write
    • Write Using the Write Mask
  • Flexible Multiprocessor Interface
  • 144-Pin PCM Quad Flat Package (QFP)
  • Class B High-Reliability Processing
  • 1-µm CMOS Technology
  • Commercial Operating Temperature Range 0°C to 70°C
  • SM34020APCM40 100-ns Instruction Cycle Time
  • Fully Programmable 32-Bit General-Purpose Processor With 512-Megabyte Linear Address Range (Bit Addressable)
  • Second-Generation Graphics System Processor (GSP)
    • Object-Code Compatible With the SM34010
    • Enhanced Instruction Set
    • Optimized Graphics Instructions
    • Coprocessor Interface
  • Pixel Processing, XY Addressing, and Window Checking Built Into the Instruction Set
  • Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit Pixel Size With 16 Boolean and Six Arithmetic Pixel Processing Options (Raster Ops)
  • 512-Byte LRU On-Chip Instruction Cache (I-Cache)
  • Optimized DRAM/Video RAM (VRAM) Interface
    • Page Mode for Burst-Memory Operations
    • Dynamic Bus Sizing (16-Bit and 32-Bit Transfers)
    • Byte-Oriented CAS Strobes
  • Flexible Host Processor Interface
    • Supports Host Transfers
    • Direct Access to All of the SM34020APCM40 Address Space
    • Implicit Addressing
    • Prefetch for Enhanced Read Access
  • Programmable CRT Control
    • Composite Synchronization Mode
    • Separate Synchronization Mode
    • Synchronization to External Synchronization
  • Direct Support for Special Features of 1M VRAMs
    • Load Write Mask
    • Load Color Mask
    • Block Write
    • Write Using the Write Mask
  • Flexible Multiprocessor Interface
  • 144-Pin PCM Quad Flat Package (QFP)

The SM34020APCM40 graphics system processor (GSP) is the second generation of an advanced high-performance CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in instruction cache (I-cache), the ability to simultaneously access memory and registers, and an instruction set designed to expedite raster graphics operations, the SM34020APCM40 provides user-programmable control of the CRT interface, as well as the memory interface [both standard DRAM and multiport video RAM (VRAM)]. The 4-gigabit (512-megabyte) physical address space is addressable on bit boundaries using variable width data fields (1 to 32 bits). Additional graphics addressing modes support 1-, 2-, 4-, 8-, 16-, and 32-bit-wide pixels.

The SM34020APCM40 graphics system processor (GSP) is the second generation of an advanced high-performance CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in instruction cache (I-cache), the ability to simultaneously access memory and registers, and an instruction set designed to expedite raster graphics operations, the SM34020APCM40 provides user-programmable control of the CRT interface, as well as the memory interface [both standard DRAM and multiport video RAM (VRAM)]. The 4-gigabit (512-megabyte) physical address space is addressable on bit boundaries using variable width data fields (1 to 32 bits). Additional graphics addressing modes support 1-, 2-, 4-, 8-, 16-, and 32-bit-wide pixels.
filter 查找其他 数字信号处理器 (DSP)
下载

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 1
类型 标题 下载最新的英语版本 日期
* 数据表 SM34020APCM40 数据表 2006年 5月 9日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点