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SCAN921821

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具有预加重功能、IEEE 1149.1 (JTAG) 和全速度 BIST 的双通道 18 位串行器

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SCAN921821

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产品详情

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (NZD) 100 100 mm² 10 x 10
  • 15-66 MHz Dual 18:1 Serializer with 2.376 Gbps Total Throughput
  • 8-level Selectable Pre-emphasis on Each Channel Drives Lossy Cables and Backplanes
  • >15kV HBM ESD Protection on Bus LVDS I/O Pins
  • Robust BLVDS Serial Data Transmission with Embedded Clock for Exceptional Noise Immunity and Low EMI
  • Power Saving Control Pin for Each Channel
  • IEEE 1149.1 "JTAG" Compliant
  • At-Speed BIST - PRBS Generation
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 260 mW (typ) Per Channel at 66 MHz with PRBS-15 Pattern
  • Single 3.3 V Supply
  • Fabricated with Advanced CMOS Process Technology
  • Industrial −40 to +85°C Temperature Range
  • Compact 100-ball NFBGA Package

All trademarks are the property of their respective owners.

  • 15-66 MHz Dual 18:1 Serializer with 2.376 Gbps Total Throughput
  • 8-level Selectable Pre-emphasis on Each Channel Drives Lossy Cables and Backplanes
  • >15kV HBM ESD Protection on Bus LVDS I/O Pins
  • Robust BLVDS Serial Data Transmission with Embedded Clock for Exceptional Noise Immunity and Low EMI
  • Power Saving Control Pin for Each Channel
  • IEEE 1149.1 "JTAG" Compliant
  • At-Speed BIST - PRBS Generation
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 260 mW (typ) Per Channel at 66 MHz with PRBS-15 Pattern
  • Single 3.3 V Supply
  • Fabricated with Advanced CMOS Process Technology
  • Industrial −40 to +85°C Temperature Range
  • Compact 100-ball NFBGA Package

All trademarks are the property of their respective owners.

The SCAN921821 is a dual channel 18-bit serializer featuring signal conditioning, boundary SCAN, and at-speed BIST. Each serializer block transforms an 18-bit parallel LVCMOS/LVTTL data bus into a single Bus LVDS data stream with embedded clock. This single serial data stream with embedded clock simplifies PCB design and reduces PCB cost by narrowing data paths that in turn reduce PCB size and layers. The single serial data stream also reduces cable size, the number of connectors, and eliminates clock-to-data and data-to-data skew.

Each channel also has an 8-level selectable pre-emphasis feature that significantly extends performance over lossy interconnect. Each channel also has its own powerdown pin that saves power by reducing supply current when the channel is not being used.

The SCAN921821 also incorporates advanced testability features including IEEE 1149.1 and at-speed BIST PRBS pattern generation to facilitate verification of board and link integrity

The SCAN921821 is a dual channel 18-bit serializer featuring signal conditioning, boundary SCAN, and at-speed BIST. Each serializer block transforms an 18-bit parallel LVCMOS/LVTTL data bus into a single Bus LVDS data stream with embedded clock. This single serial data stream with embedded clock simplifies PCB design and reduces PCB cost by narrowing data paths that in turn reduce PCB size and layers. The single serial data stream also reduces cable size, the number of connectors, and eliminates clock-to-data and data-to-data skew.

Each channel also has an 8-level selectable pre-emphasis feature that significantly extends performance over lossy interconnect. Each channel also has its own powerdown pin that saves power by reducing supply current when the channel is not being used.

The SCAN921821 also incorporates advanced testability features including IEEE 1149.1 and at-speed BIST PRBS pattern generation to facilitate verification of board and link integrity
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类型 标题 下载最新的英语版本 日期
* 数据表 SCAN921821 Dual 18-Bit Serializer w/Pre-emph, IEEE 1149.1 JTAG & At-Speed BIST 数据表 (Rev. C) 2013年 4月 15日
应用手册 External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A) 2013年 4月 26日
设计指南 18-bit SerDes Design Guide (DS92LV18, SCAN921821) 2007年 3月 29日

设计和开发

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仿真模型

SCAN921821 IBIS Model

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