SBOS673 September 2017 OPA837

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics: VS = 5 V
    6. 6.6Electrical Characteristics: VS = 3 V
    7. 6.7Typical Characteristics: VS = 5.0 V
    8. 6.8Typical Characteristics: VS = 3.0 V
    9. 6.9Typical Characteristics: ±2.5-V to ±1.5-V Split Supply
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagrams
    3. 7.3Feature Description
      1. 7.3.1OPA837 Comparison
      2. 7.3.2Input Common-Mode Voltage Range
      3. 7.3.3Output Voltage Range
      4. 7.3.4Power-Down Operation
      5. 7.3.5Low-Power Applications and the Effects of Resistor Values on Bandwidth
      6. 7.3.6Driving Capacitive Loads
    4. 7.4Device Functional Modes
      1. 7.4.1Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 7.4.2Single-Supply Operation (2.7 V to 5.4 V)
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1 Noninverting Amplifier
      2. 8.1.2 Inverting Amplifier
      3. 8.1.3 Output DC Error Calculations
      4. 8.1.4 Output Noise Calculations
      5. 8.1.5 Instrumentation Amplifier
      6. 8.1.6 Attenuators
      7. 8.1.7 Differential to Single-Ended Amplifier
      8. 8.1.8 Differential-to-Differential Amplifier
      9. 8.1.9 Pulse Application With Single-Supply Circuit
      10. 8.1.10ADC Driver Performance
    2. 8.2Typical Applications
      1. 8.2.1Active Filters
        1. 8.2.1.1Design Requirements
        2. 8.2.1.2Detailed Design Procedure
        3. 8.2.1.3Application Curves
      2. 8.2.2Implementing a 2:1 Active Multiplexer
        1. 8.2.2.1Design Requirements
        2. 8.2.2.2Detailed Design Procedure
      3. 8.2.31-Bit PGA Operation
        1. 8.2.3.1Design Requirements
        2. 8.2.3.2Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Receiving Notification of Documentation Updates
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VS– to VS+ Supply voltage5.5V
Supply turn-on/off maximum dV/dT(2) 1V/µs
VI Input voltageVS– – 0.5VS+ + 0.5V
VID Differential input voltage±1V
II Continuous input current±10mA
IO Continuous output current(3) ±20mA
Continuous power dissipationSee Thermal Information
TJ Maximum junction temperature150°C
TA Operating free-air temperature–40125°C
Tstg Storage temperature–65150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Staying below this ± supply turn-on edge rate prevents the edge-triggered ESD absorption device across the supply pins from turning on.
Long-term continuous output current for electromigration limits.

ESD Ratings

VALUEUNIT
V(ESD) Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
VS+ Single-supply voltage2.755.4V
TA Ambient temperature–4025125°C

Thermal Information

THERMAL METRIC(1) OPA837UNIT
DBV
(SOT23-6)
DCK
(SC70)
6 PINS5 PINS
RθJA Junction-to-ambient thermal resistance194203°C/W
RθJCtop Junction-to-case (top) thermal resistance129152°C/W
RθJB Junction-to-board thermal resistance3976°C/W
ψJT Junction-to-top characterization parameter2658°C/W
ψJB Junction-to-board characterization parameter3976°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics: VS = 5 V

at VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNITTEST LEVEL(1)
AC PERFORMANCE
SSBWSmall-signal bandwidthVOUT = 20 mVPP, G = 190105MHzC
VOUT = 20 mVPP, G = 245C
VOUT = 20 mVPP, G = 105C
GBPGain-bandwidth productVOUT = 20 mVPP, G = 104550MHzC
LSBWLarge-signal bandwidthVOUT = 2 VPP, G = 226MHzC
Bandwidth for 0.1-dB flatnessVOUT = 200 mVPP, G = 26MHzC
SRSlew rateFrom LSBW(2) 105V/µsC
tR, tF Rise, fall timeVOUT = 0.5-V step, G = 2, input tR = 10ns1011nsC
OvershootVOUT = 2-V step, G = 2, input tR = 40 ns7.0%C
Settling time to 0.1%VOUT = 2.0-V step, G = 1, input tR = 4 ns25nsC
Settling time to 0.01%VOUT = 2.0-V step, G = 1, input tR = 4 ns40nsC
HD2Second-order harmonic distortionf = 100 kHz, VO = 2 VPP, G = 1 (see Figure 73)–120dBcC
HD3Third-order harmonic distortionf = 100 kHz, VO = 2 VPP, G = 1 (see Figure 73)–145dBcC
Input voltage noisef = 500 Hz4.7nV/√Hz C
Voltage noise 1/f corner frequencySee Figure 3935HzC
Input current noisef = 20 kHz0.4pA/√Hz C
Current noise 1/f corner frequencySee Figure 395kHzC
Overdrive recovery timeG = 2, 2x output overdrive (see Figure 30)75nsC
Closed-loop output impedancef = 1 MHz, G = 1 (see Figure 38)0.14ΩC
DC PERFORMANCE
AOL Open-loop voltage gainVO = ±2 V, RL = 2 kΩ120135dBA
Input-referred offset voltageTA ≈ 25°C–130±30130µVA
TA = 0°C to +70°C (DCK package)–170±30200B
TA = –40°C to +85°C (DCK package)–234±30226B
TA = –40°C to +125°C (DCK package)–234±30290B
Input offset voltage drift(4) DCK package, TA = –40°C to +125°C–1.6±0.41.6µV/°CB
Input offset voltage drift(4) DBV package, TA = –40°C to +125°C–2.0±0.42.0µV/°CB
Input bias current(3) TA ≈ 25°C150340520nAA
TA = 0°C to +70°C50340664B
TA = –40°C to +85°C50340718B
TA = –40°C to +125°C50340850B
Input bias current drift(4) TA = –40°C to +125°C0.81.53.3nA/°CB
Input offset currentTA ≈ 25°C–40±640nAA
TA = 0°C to +70°C–46±652B
TA = –40°C to +85°C–56±655B
TA = –40°C to +125°C–56±665B
Input offset current drift(4) TA = –40°C to +125°C–250±40250pA/°CB
INPUT
Common-mode input range, lowTA ≈ 25°C, < 3-dB degradation in CMRR limit–0.20VA
TA = –40°C to +125°C, < 3-dB degradation in CMRR limit–0.20B
Common-mode input range, highTA ≈ 25°C, < 3-dB degradation in CMRR limit3.73.8VA
TA = –40°C to +125°C, < 3-dB degradation in CMRR limit3.73.8B
CMRRCommon-mode rejection ratio95110dBA
Input impedance common-mode250 || 1.5kΩ || pFC
Input impedance differential mode180 || 0.5kΩ || pFC
OUTPUT
VOL Output voltage, lowTA ≈ 25°C, G = 20.050.1VA
TA = –40°C to +125°C, G = 50.050.1B
VOH Output voltage, highTA ≈ 25°C, G = 24.94.95VA
TA = –40°C to +125°C, G = 54.84.9B
Maximum current into a resistive loadTA ≈ 25°C, ±1.6 V into 27 Ω, VIO < 2 mV±58±70mAA
Linear current into a resistive loadTA ≈ 25°C, ±1.7 V into 37.4 Ω, AOL > 80 dB±45±50mAA
Linear current into a resistive load overtemperatureTA = –40°C to +125°C, ±1.31 V into 37.4 Ω, AOL > 80 dB±35±45mAC
Closed-loop output impedanceGain of 1 V/V, ±30-mA DC0.6.C
POWER SUPPLY
Specified operating voltage2.75.4VB
Quiescent operating current per amplifier (5-V supply)TA ≈ 25°C(5) 564592625µAA
TA = –40°C to +125°C408592865B
Supply current temperature coefficientTA = –40°C to +125°C (see Figure 57)1.11.92.4µA/°CB
+PSRRPositive power-supply rejection ratio95110dBA
–PSRRNegative power-supply rejection ratio92108dBA
POWER DOWN (Pin Must be Driven)
Enable voltage thresholdSpecified on above VS– + 1.5 V1.5VA
Disable voltage thresholdSpecified off below VS– + 0.55 V0.55VA
Power-down pin bias current PD = 0 V to VS+ –5050nAA
Power-down quiescent current PD ≤ 0.55 V4510µAA
Power-down quiescent current over temperature PD ≤ 0.55 V, TA = –40°C to +125°C10µAB
Turnon time delayTime from PD = high to VOUT = 90% of final value300nsC
Turnoff time delayTime from PD = low to VOUT = 10% of original value100nsC
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (0.8 × VPEAK / √2) × 2π × f–3dB where this f–3dB is the typical measured 2-VPP bandwidth at gains of 1 V/V.
Current is considered positive out of the pin.
Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range. Typical drift specifications are ±1σ. Maximum drift specifications are set by the min, max sample packaged test data using a wafer-level screened drift. Min, max drift is not specified by final automated test equipment (ATE) nor by QA sample testing.
The typical specification is at 25°C TJ. The min, max limits are expanded for the automated test equipment (ATE) to account for an ambient range from 22°C to 32°C with a 2-µA/°C temperature coefficient on the supply current.

Electrical Characteristics: VS = 3 V

at VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNITTEST LEVEL(1)
AC PERFORMANCE
SSBWSmall-signal bandwidthVOUT = 20 mVPP, G = 185105MHzC
VOUT = 20 mVPP, G = 245C
VOUT = 20 mVPP, G = 105C
GBPGain-bandwidth productVOUT = 20 mVPP, G = 104050MHzC
LSBWLarge-signal bandwidthVOUT = 1 VPP, G = 230MHzC
Bandwidth for 0.1-dB flatnessVOUT = 200 mVPP, G = 26MHzC
SRSlew rateFrom LSBW(2) 65V/µsC
tR, tF Rise, fall timeVOUT = 0.5-V step, G = 2, input tR = 10 ns1011nsC
OvershootVOUT = 2-V step, G = 2, input tR = 40 ns7%C
Settling time to 0.1%VOUT = 0.5-V step, G = 1, input tR = 4 ns35nsC
Settling time to 0.01%VOUT = 0.5-V step, G = 1, input tR = 4 ns50nsC
HD2Second-order harmonic distortionf = 100 kHz, VO = 1 VPP, G = 1 (see Figure 73)–125dBcC
HD3Third-order harmonic distortionf = 100 kHz, VO = 1 VPP, G = 1 (see Figure 73)–138dBcC
Input voltage noisef = 500 Hz4.9nV/√Hz C
Voltage noise 1/f corner frequencySee Figure 3935HzC
Input current noisef = 10 kHz0.4pA/√Hz C
Current noise 1/f corner frequencySee Figure 395kHzC
Overdrive recovery timeG = 2, 2x output overdrive (see Figure 29)65nsC
Closed-loop output impedancef = 1 MHz, G = 1 (see Figure 38).14ΩC
DC PERFORMANCE
AOL Open-loop voltage gainVO = ±1 V, RL = 2 kΩ120133dBA
Input-referred offset voltageTA ≈ 25°C–130±30130µVA
TA = 0°C to +70°C–170±30200B
TA = –40°C to +85°C–234±30226B
TA = –40°C to +125°C–234±30290B
Input offset voltage drift(4) DCK package, TA = –40°C to +125°C–1.6±0.41.6µV/°CB
Input offset voltage driftDBV package, TA = –40°C to +125°C–2.0±0.42.0µV/°CB
Input bias current(3) TA ≈ 25°C145320510nAA
TA = 0°C to +70°C50320659B
TA = –40°C to +85°C50320708B
TA = –40°C to +125°C50320840B
Input bias current drift(4) TA = –40°C to +125°C0.81.53.3nA/°CB
Input offset currentTA ≈ 25°C–40±640nAA
TA = 0°C to +70°C–46±652B
TA = –40°C to +85°C–56±655B
TA = –40°C to +125°C–56±665B
Input offset current drift(4) TA = –40°C to +125°C–250±40250pA/°CB
INPUT
Common-mode input range, lowTA ≈ 25°C, < 3-dB degradation in CMRR limit–0.20VA
TA = –40°C to +125°C, < 3-dB degradation in CMRR limit–0.20B
Common-mode input range, highTA ≈ 25°C, < 3-dB degradation in CMRR limit3.83.9VA
TA = –40°C to +125°C, < 3-dB degradation in CMRR limit3.83.9B
CMRRCommon-mode rejection ratio90105dBA
Input impedance common-mode250 || 1.5kΩ || pFC
Input impedance differential mode180 || 0.5kΩ || pFC
OUTPUT
VOL Output voltage, lowTA ≈ 25°C, G = 20.050.1VA
TA = –40°C to +125°C, G = 20.100.2B
VOH Output voltage, highTA ≈ 25°C, G = 24.94.95VA
TA = –40°C to +125°C, G = 24.804.9B
Maximum current into a resistive loadTA ≈ 25°C, ±0.8 V into 17.5 Ω, VIO < 2 mV±45±55mAA
Linear current into a resistive loadTA ≈ 25°C, ±0.9 V into 21.5 Ω, AOL > 80 dB±40±45mAA
Linear current into a resistive load overtemperatureTA = –40°C to +125°C, ±0.7 V into 21.5 Ω, AOL > 80 dB±32±40BΩC
POWER SUPPLY
Specified operating voltage2.75.4VB
Quiescent operating current per amplifier (3-V supply)TA ≈ 25°C(1) 547570607µAA
TA = –40°C to +125°C404570817B
Supply current temperature coefficientTA = –40°C to +125°C (see Figure 57)0.81.72.2µA/°CB
+PSRRPositive power-supply rejection ratio90110dBA
–PSRRNegative power-supply rejection ratio88105dBA
POWER DOWN (Pin Must be Driven)
Enable voltage thresholdSpecified on above VS– + 1.5 V1.5VA
Disable voltage thresholdSpecified off below VS– + 0.55 V0.55VA
Power-down pin bias current PD = 0 V to VS+ –5050nAA
Power-down quiescent current PD ≤ 0.55 V138µAA
Power-down quiescent current over temperature PD ≤ 0.55 V, TA = –40°C to +125°C8µAB
Turnon time delayTime from PD = high to VOUT = 90% of final value300nsC
Turnoff time delayTime from PD = low to VOUT = 10% of original value100nsC
The typical specification is at 25°C TJ. The min, max limits are expanded for the automated test equipment (ATE) to account for an ambient range from 22°C to 32°C with a 4-µA/°C temperature coefficient on the supply current.

Typical Characteristics: VS = 5.0 V

at VS+ = 5.0 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless otherwise noted)
OPA837 D001_SBOS673.gif
See Figure 73 and Table 2, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 1. Noninverting Small-Signal Frequency Response
vs Gain
OPA837 D003_SBOS673.gif
Gain = 2 V/V, RLOAD = 2 kΩ
Figure 3. Noninverting Large-Signal Bandwidth vs VOPP
OPA837 D005_SBOS673.gif
See Figure 73 and Table 2, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 5. Noninverting Response Flatness vs Gain
OPA837 D007_SBOS673.gif
See Figure 73, gain = 2 V/V,
input edge rate set to stay below slew limiting
Figure 7. Noninverting Step Response vs Time and VOPP
OPA837 D009_SBOS673.gif
See Figure 73 and Table 2
Figure 9. Simulated Noninverting Settling Time
OPA837 D011_SBOS673.gif
See Figure 73 and Table 2, gain = 2 V/V
Figure 11. Noninverting Overdrive Recovery
OPA837 D013_SBOS673.gif
See Figure 73, Figure 74, Table 2, and Table 3, VO = 2 VPP
Figure 13. Harmonic Distortion vs Frequency
OPA837 D015_SBOS673.gif
See Figure 73, Figure 74, Table 2, and Table 3, VO = 2 VPP,
f = 100 kHz
Figure 15. Harmonic Distortion vs Output Voltage
OPA837 D017_SBOS673.gif
See Figure 86, VO = 2 VPP, f = 100 kHz
Figure 17. Harmonic Distortion as Active Mux
OPA837 D002_SBOS673.gif
See Figure 74 and Table 3, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 2. Inverting Small-Signal Frequency Response
vs Gain
OPA837 D004_SBOS673.gif
Gain = –1 V/V, RLOAD = 2 kΩ
Figure 4. Inverting Large-Signal Bandwidth vs VOPP
OPA837 D006_SBOS673.gif
See Figure 74 and Table 3, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 6. Inverting Response Flatness vs Gain
OPA837 D008_SBOS673.gif
See Figure 74, gain = –1 V/V,
input edge rate set to stay below slew limiting
Figure 8. Inverting Step Response vs Time and VOPP
OPA837 D010_SBOS673.gif
See Figure 74 and Table 3
Figure 10. Simulated Inverting Settling Time
OPA837 D012_SBOS673.gif
See Figure 73 and Table 3, gain –1 V/V
Figure 12. Inverting Overdrive Recovery
OPA837 D014_SBOS673.gif
See Figure 73, Figure 74, Table 2, and Table 3, VO = 2 VPP,
f = 100 kHz
Figure 14. Harmonic Distortion vs RLOAD
OPA837 D016_SBOS673.gif
See Figure 73, Figure 74, Table 2, and Table 3, VO = 2 VPP,
f = 100 kHz
Figure 16. Harmonic Distortion vs Gain Magnitude
OPA837 D018_SBOS673.gif
See Figure 86, gain of 1 V/V or 2 V/V, VO = 2 VPP,
f = 100 kHz
Figure 18. Harmonic Distortion as 1-Bit PGA

Typical Characteristics: VS = 3.0 V

at VS+ = 3.0 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless otherwise noted)
OPA837 D019_SBOS673.gif
See Figure 73 and Table 2, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 19. Noninverting Small-Signal Response vs Gain
OPA837 D021_SBOS673.gif
See Figure 73, gain = 2 V/V
Figure 21. Noninverting Large-Signal Bandwidth vs VOPP
OPA837 D023_SBOS673.gif
See Figure 73 and Table 2, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 23. Noninverting Response Flatness vs Gain
OPA837 D025_SBOS673.gif
See Figure 73 and Table 2, gain = 2 V/V,
input edge rate set to stay below slew limiting
Figure 25. Noninverting Step Response vs VOPP
OPA837 D027_SBOS673.gif
See Figure 73 and Table 2
Figure 27. Simulated Noninverting Settling Time
OPA837 D029_SBOS673.gif
See Figure 73 and Table 2, gain = 2 V/V
Figure 29. Noninverting Overdrive Recovery
OPA837 D031_SBOS673.gif
See Figure 73, Figure 74, Table 2, and Table 3, VO = 1 VPP, RLOAD = 2 kΩ
Figure 31. Harmonic Distortion vs Frequency
OPA837 D033_SBOS673.gif
See Figure 73, Figure 74, Table 2, and Table 3, RLOAD = 2 kΩ,
f = 100 kHz
Figure 33. Harmonic Distortion vs Output Swing
OPA837 D035_SBOS673.gif
See Figure 86, gain = 1 V/V, VOUT = 1 VPP, RLOAD = 2 kΩ
Figure 35. Harmonic Distortion as Active Mux
OPA837 D020_SBOS673.gif
See Figure 74 and Table 3, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 20. Inverting Small-Signal Response vs Gain
OPA837 D022_SBOS673.gif
See Figure 74, gain = –1 V/V
Figure 22. Inverting Large-Signal Bandwidth vs VOPP
OPA837 D024_SBOS673.gif
See Figure 74 and Table 3, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 24. Inverting Response Flatness vs Gain
OPA837 D026_SBOS673.gif
See Figure 74 and Table 3, gain = –1 V/V,
input edge rate set to stay below slew limiting
Figure 26. Inverting Step Response vs VOPP
OPA837 D028_SBOS673.gif
See Figure 74 and Table 3
Figure 28. Simulated Inverting Settling Time
OPA837 D030_SBOS673.gif
See Figure 74 and Table 3, gain = –1 V/V
Figure 30. Inverting Overdrive Recovery
OPA837 D032_SBOS673.gif
See Figure 73, Figure 74, Table 2, and Table 3, VO = 2 VPP,
f = 100 kHz, RLOAD = 2 kΩ
Figure 32. Harmonic Distortion vs RLOAD
OPA837 D034_SBOS673.gif
See Figure 73, Figure 74, Table 2, and Table 3, RLOAD = 2 kΩ,
f = 100 kHz, VOUT = 2 VPP
Figure 34. Harmonic Distortion vs Gain Magnitude
OPA837 D036_SBOS673.gif
See Figure 87, gain of 1 V/V and 2 V/V, VOUT = 1 VPP,
RLOAD = 2 kΩ
Figure 36. Harmonic Distortion as 1-Bit PGA

Typical Characteristics: ±2.5-V to ±1.5-V Split Supply

with PD = VCC and TA ≈ 25°C (unless otherwise noted)
OPA837 D037_SBOS673.gif
No load simulation
Figure 37. Open-Loop Gain and Phase vs Frequency
OPA837 D039_SBOS673.gif
Measured then fit to ideal 1/f model
Figure 39. Input Spot Noise Density vs Frequency
OPA837 D041_SBOS673.gif
Simulated curves
Figure 41. CMRR and PSRR vs Frequency
OPA837 D043_SBOS673.gif
830 units at each supply voltage
Figure 43. Input Offset Voltage Distribution
OPA837 D045_SBOS673.gif
50 units at 5-V and 3-V supply
Figure 45. Input Offset Voltage vs Ambient Temperature
OPA837 D047_SBOS673.gif
–40°C to +125°C fit, 82 units, DBV package
Figure 47. Input Offset Voltage Drift Distribution
OPA837 D049_SBOS673.gif
See Figure 65 and Table 2, small signal,
targeting 30° phase margin
Figure 49. Output Resistor vs CLOAD
OPA837 D051_SBOS673.gif
Figure 51. Turn-On Time to Sinusoidal Input
OPA837 D053_SBOS673.gif
Figure 53. Gain of 1 Turn-On Time to Final DC Value at Midscale (Simulated)
OPA837 D055_SBOS673.gif
Figure 55. Output Voltage Swing vs Load Resistor
OPA837 D057_SBOS673.gif
50 units at 5-V and 3-V supply
Figure 57. Supply Current vs Ambient Temperature
OPA837 D059_SBOS673.gif
12 units, 5-V and 3-V supplies
Figure 59. Input Offset Voltage vs
Input Common-Mode Voltage
OPA837 D038_SBOS673.gif
Figure 73 and Table 2 (simulation)
Figure 38. Closed-Loop Output Impedance vs Frequency
OPA837 D040_SBOS673.gif
Input-referred voltage noise RS = 0 Ω
Figure 40. Low-Frequency Voltage Noise vs Time
OPA837 D042_SBOS673.gif
Figure 42. Disabled Isolation Noninverting Input to Output vs Frequency
OPA837 D044_SBOS673.gif
830 units at each supply voltage
Figure 44. Input Offset Current Distribution
OPA837 D046_SBOS673.gif
50 units at 5-V and 3-V supply
Figure 46. Input Offset Current vs Ambient Temperature
OPA837 D048_SBOS673.gif
–40°C to +125°C fit, 82 units, DBV package
Figure 48. Input Offset Current Drift Distribution
OPA837 D050_SBOS673.gif
Figure 50. Small-Signal Frequency Response vs CLOAD
With Recommended ROUT
OPA837 D052_SBOS673.gif
Figure 52. Turn-Off Time to Sinusoidal Input
OPA837 D054_SBOS673.gif
Figure 54. Gain of 2 Turn-On Time to Final DC Value at Midscale (Simulated)
OPA837 D056_SBOS673.gif
Figure 56. Output Saturation Voltage vs Load Current
OPA837 D058_SBOS673.gif
Figure 58. Supply Current vs Power-Down Voltage
(Turn-On Higher Than Turn-Off)
OPA837 D060_SBOS673.gif
Measured single device, 5-V and 3-V supplies
Figure 60. Input Bias and Offset Current vs VICM