SBOS673 September 2017 OPA837


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics: VS = 5 V
    6. 6.6Electrical Characteristics: VS = 3 V
    7. 6.7Typical Characteristics: VS = 5.0 V
    8. 6.8Typical Characteristics: VS = 3.0 V
    9. 6.9Typical Characteristics: ±2.5-V to ±1.5-V Split Supply
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagrams
    3. 7.3Feature Description
      1. 7.3.1OPA837 Comparison
      2. 7.3.2Input Common-Mode Voltage Range
      3. 7.3.3Output Voltage Range
      4. 7.3.4Power-Down Operation
      5. 7.3.5Low-Power Applications and the Effects of Resistor Values on Bandwidth
      6. 7.3.6Driving Capacitive Loads
    4. 7.4Device Functional Modes
      1. 7.4.1Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 7.4.2Single-Supply Operation (2.7 V to 5.4 V)
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1 Noninverting Amplifier
      2. 8.1.2 Inverting Amplifier
      3. 8.1.3 Output DC Error Calculations
      4. 8.1.4 Output Noise Calculations
      5. 8.1.5 Instrumentation Amplifier
      6. 8.1.6 Attenuators
      7. 8.1.7 Differential to Single-Ended Amplifier
      8. 8.1.8 Differential-to-Differential Amplifier
      9. 8.1.9 Pulse Application With Single-Supply Circuit
      10. 8.1.10ADC Driver Performance
    2. 8.2Typical Applications
      1. 8.2.1Active Filters
        1. Requirements
        2. Design Procedure
        3. Curves
      2. 8.2.2Implementing a 2:1 Active Multiplexer
        1. Requirements
        2. Design Procedure
      3. 8.2.31-Bit PGA Operation
        1. Requirements
        2. Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Receiving Notification of Documentation Updates
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information


Layout Guidelines

The OPA837EVM can be used as a reference when designing the circuit board. TI recommends following the EVM layout of the external components near to the amplifier, ground plane construction, and power routing as closely as possible. General guidelines are listed below:

  1. Signal routing must be direct and as short as possible into an out of the op amp.
  2. The feedback path must be short and direct avoiding vias if possible, especially with G = 1 V/V.
  3. Ground or power planes must be removed from directly under the negative input and output pins of the amplifier.
  4. TI recommends placing a series output resistor as close to the output pin as possible. See Figure 49 for recommended values for the expected capacitive load. These values are derived targeting a 30° phase margin to the output of the op amp.
  5. A 2.2-µF power-supply decoupling capacitor must be placed within two inches of the device and can be shared with other op amps. For split supply, a capacitor is required for both supplies.
  6. A 0.1-µF power-supply decoupling capacitor must be placed as close to the supply pins as possible, preferably within 0.1 inch. For split supply, a capacitor is required for both supplies.
  7. The PD pin uses low logic swing levels. If the pin is not used, PD must be tied to the positive supply to enable the amplifier. If the pin is used, PD must be actively driven. A bypass capacitor is not necessary, but can be used for robustness in noisy environments.

Layout Example

OPA837 sbos867_evm_dwg.gif Figure 88. EVM Layout Example