SBOS673 September 2017 OPA837
The OPA837 is a power efficient, unity-gain stable, voltage-feedback amplifier (VFA). Combining a negative rail input stage and a rail-to-rail output (RRO) stage, the OPA837 provides a flexible solution where exceptional precision and wide bandwidth at low power are required. This 50-MHz gain bandwidth product (GBP) amplifier requires less than 0.65 mA of supply current over a 2.7-V to 5.4-V total supply operating range. A shutdown feature on the 6-pin package version provides power savings where the system requires less than 10 µA when shut down. Offering a unity-gain bandwidth greater than 100 MHz, the OPA837 provides less than –118-dBc THD at 100 kHz and a 2-VPP output.
The OPA837 is a standard voltage-feedback op amp with two high-impedance inputs and a low-impedance output. Figure 61 and Figure 62 show the supported standard applications circuits. These application circuits are shown with a DC VREF on the inputs that set the DC operating points for single-supply designs. The VREF is often ground, especially for split-supply applications.
Table 1 lists several members of the device family that includes the OPA837.
|PART NUMBER||Av = +1 BANDWIDTH (MHz)||5-V IQ|
(mA, Max 25°C)
|INPUT NOISE VOLTAGE|
(dBc, 100 kHz)
When the primary design goal is a linear amplifier with high CMRR, the design must remain within the input common-mode voltage range (VICR) of an op amp. These ranges are referenced off of each supply as an input headroom requirement. Ensured operation at 25°C is maintained to the negative supply voltage and to within 1.3 V of the positive supply voltage. The common-mode input range specifications in the Electrical Characteristics table use CMRR to set the limit. The limits are selected to ensure CMRR does not degrade more than 3 dB below the minimum CMRR value if the input voltage is within the specified range.
Assuming the op amp is in linear operation, the voltage difference between the input pins is small (ideally 0 V); and the input common-mode voltage is analyzed at either input pin with the other input pin assumed to be at the same potential. The voltage at VIN+ is simple to evaluate. In the noninverting configuration of Figure 61, the input signal, VIN, must not violate the VICR. In the inverting configuration of Figure 62, the reference voltage, VREF, must be within the VICR.
The input voltage limits have fixed headroom to the power rails and track the power-supply voltages. For one 5-V supply, the typical linear input voltage ranges from –0.2 V to 3.8 V and –0.2 V to 1.5 V for a 2.7-V supply. The delta headroom from each power-supply rail is the same in either case: –0.2 V and 1.2 V, respectively.
The OPA837 is a rail-to-rail output op amp. Rail-to-rail output typically means that the output voltage swings to within 100 mV of the supply rails. There are two different ways to specify this feature: one is with the output still in linear operation and another is with the output saturated. Saturated output voltages are closer to the power-supply rails than the linear outputs, but the signal is not a linear representation of the input. Saturation and linear operation limits are affected by the output current, where higher currents lead to more voltage loss in the output transistors; see Figure 55.
The Electrical Characteristics tables list saturated output voltage specifications with a 2-kΩ load. Figure 55 illustrates the saturated voltage-swing limits versus output load resistance, and Figure 56 illustrates the output saturation voltage versus load current. Given a light load, the output voltage limits have nearly constant headroom to the power rails and track the power-supply voltages. For example, with a 2-kΩ load and a single
5-V supply, the linear output voltage ranges from 0.10 V to 4.9 V and ranges from 0.1 V to 2.6 V for a 2.7-V supply. The delta from each power-supply rail is the same in either case: 0.1 V.
With devices like the OPA837 where the input range is lower than the output range, typically the input limits the available signal swing only in a noninverting gain of 1 V/V. Signal swing in noninverting configurations in gains greater than +1 V/V and inverting configurations in any gain are typically limited by the output voltage limits of the op amp.
The OPA837 includes a power-down mode in the 6-pin SOT23-6 package. Under logic control, the amplifier can switch from normal operation to a standby current of less than 10 µA. When the PD pin is connected high, the amplifier is active. Connecting the PD pin low disables the amplifier and places the output in a high-impedance state. When the amplifier is configured as a unity-gain buffer, the output stage is in a high DC-impedance state. A new feature in the OPA837 is a switch from the external inverting input pin to the internal active transistors. This switch operates with the disable pin function to open up the connection to the internal devices when powered down. Operating in unity gain provides a high-impedance voltage into both the output and inverting input pins. This feature allows direct active multiplexer operation to be implemented; see Figure 86. When disabled, the internal input devices on the inverting input approximately follow the noninverting input on the other side of the open switch through the back-to-back protection diodes across the inputs. When powered up, these diodes (two in each direction) act to limit overdrive currents into the active transistors.
The PD pin must be actively driven high or low and must not be left floating. If the power-down mode is not used, PD must be tied to the positive supply rail.
PD logic states are referenced relatively low to the negative supply rail, VS–. When the op amp is powered from a single-supply and ground, and the disable line is driven from logic devices with similar VDD voltages to the op amp, the disable operation does not require any special consideration. The OPA837 is specified to be off with PD driven to within 0.55 V of the negative supply and specified to be on when driven more than 1.5 V above the negative supply. Slight hysteresis is provided around a nominal 1-V switch point; see Figure 58. When the op amp is powered from a split supply with VS– below ground, a level shift logic swing below ground is required to operate the disable function.
The OPA837 can use a direct short in the feedback for a gain of 1 V/V. Table 2 gives a list of recommended values over gain for an increasing noninverting gain target. This table was produced by increasing the R values until they added 50% of the total output noise power. Higher values can be used to reduce power at the cost of higher noise. Lower values can be used to reduce the total output noise at the cost of more load power in the feedback network. Stability is also impaired going to very high values because of the pole introduced into the feedback path with the inverting input capacitance (1.5-pF common-mode). In low-power applications, reducing the current in the feedback path is preferable by increasing the resistor values. Using larger value resistors has two primary side effects (other than lower power) because of the interactions with the inverting input parasitic capacitance. Using large value resistors lowers the bandwidth and lowers the phase margin. When the phase margin is lowered, peaking in the frequency response and overshoot and ringing in the pulse response results.
Figure 63 shows the gain = 2 V/V (6 dB) small-signal frequency response with RF and RG equal to 1 kΩ, 2 kΩ, 5 kΩ, 10 kΩ, and 20 kΩ. This test was done with RL = 2 kΩ. Lower RL values can reduce the peaking because of RL loading effects, but higher values do not have a significant effect.
As expected, larger value resistors cause lower bandwidth and peaking in the response (peaking in frequency response is synonymous with overshoot and ringing in pulse response). Adding a 1.5-pF capacitor in parallel with RF (equal to the input common-mode capacitance) helps compensate the phase margin loss and restores flat frequency response. Figure 64 shows the test circuit.
The OPA837 can drive a parasitic load capacitance up through 4 pF on the output with no special considerations. When driving capacitive loads greater than 4 pF, TI recommends using a small resistor (RO) in series with the output as close to the device as possible. Without RO, output capacitance interacts with the output impedance of the amplifier causing phase shift in the loop gain of the amplifier that reduces the phase margin. This reduction causes peaking in the frequency response and overshoot and ringing in the pulse response. Inserting RO isolates the phase shift from the loop-gain path and restores the phase margin; however RO can also limit bandwidth to the capacitive load.
Figure 65 shows the test and Figure 49 illustrates the recommended values of RO versus capacitive loads, CL using a 30° phase margin target for the op amp. See Figure 50 for the frequency responses with various values of CL and ROUT parametric on gain.
To facilitate testing with common lab equipment, the OPA837EVM (see the OPA837DBV and OPA836DBV EVM User's Guide) allows split-supply operation. This configuration eases lab testing because the mid-point between the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum analyzers, and other lab equipment have inputs and outputs that prefer a ground reference for DC-coupled testing.
Figure 66 shows a simple noninverting configuration analogous to Figure 61 with a ±2.5-V supply and VREF equal to ground. The input and output swing symmetrically around ground. For ease of use, split supplies are preferred in systems where signals swing around ground. In this example, an optional bias current cancellation resistor is used in series with the noninverting input. For DC-coupled applications, set this resistor to be equal to the parallel combination of RF and RG. This resistor increases the noise contribution at the input because of that resistor noise (see the Output Noise Calculations section).
Figure 67 shows the step response for this gain of 2-V/V circuit with a ±1-V input to a ±2-V output. For a 4-V output step, the input edge rate is set to 40 ns to avoid slew limiting.
Most newer systems use a single power supply to improve efficiency and to simplify power-supply design. The OPA837 can be used with single-supply power (ground for the negative supply) with no change in performance from split supply, as long as the input and output pins are biased within the linear operating region of the device. The outputs nominally swing rail-to-rail with approximately a 100-mV headroom required for linear operation. The inputs can typically swing 0.2 V below the negative rail (typically ground) and to within 1.2 V of the positive supply. For DC-coupled single-supply operation, the input swing is below the available output swing range for noninverting gains greater than 1.30 V/V. Typically, the 1.2-V input headroom required to the positive supply only limits output swing range for a unity-gain buffer.
To change the circuit from split supply to single-supply, level shift all voltages by half the difference between the power-supply rails. For example, Figure 68 depicts changing from a ±2.5-V split supply to a 5-V single-supply. The load is shown as mid-supply referenced but can be grounded as well.
A practical circuit has an amplifier or other circuit providing the bias voltage for the input, and the output of this amplifier stage provides the bias for the next stage.
Figure 69 shows a typical noninverting amplifier circuit. With 5-V single-supply, a mid-supply reference generator is needed to bias the negative side through RG. To cancel the voltage offset that is otherwise caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if a gain of 2 V/V is required and RF = 2 kΩ, select RG = 2 kΩ to set the gain, and R1 = 1 kΩ for bias current cancellation which reduces the output DC error to IOS × RF. The value for C is dependent on the reference, and TI recommends a value of at least 0.1 µF to limit noise. The frequency response flatness is impacted by the AC impedance, including the reference and capacitor added to the RG element.
Figure 70 shows a similar noninverting single-supply scenario with the reference generator replaced by the Thevenin equivalent using resistors and the positive supply. RG’ and RG” form a resistor divider from the 5-V supply and are used to bias the negative side with the parallel sum equal to the equivalent RG to set the gain. To cancel the voltage offset that is otherwise caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG’ in parallel with RG” (R1= RF || RG’ || RG”). For example, if a gain of 2 V/V is required and RF = 2 kΩ, selecting RG’ = RG” = 4 kΩ gives an quivalent parallel sum of 2 kΩ, sets the gain to 2, and references the input to mid-supply (2.5 V). R1 is set to 1 kΩ for bias current cancellation. The resistor divider costs less than the 2.5-V reference in Figure 69 but increases the current from the 5-V supply. Any noise or variation on the 5-V supply now also comes into the circuit as an input through the biasing path.
Figure 71 shows a typical inverting amplifier circuit. With a 5-V single supply, a mid-supply reference generator is needed to bias the positive side through R1. To cancel the voltage offset that is otherwise caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if a gain of –2 V/V is required and RF = 2 kΩ, select RG = 1 kΩ to set the gain and R1 = 667 Ω for bias current cancellation. The value for C is dependent on the reference, but TI recommends a value of at least 0.1 µF to limit noise into the op amp.
Figure 72 shows a similar inverting single-supply scenario with the reference generator replaced by the Thevenin equivalent using resistors and the positive supply. R1 and R2 form a resistor divider from the 5-V supply and are used to bias the positive side. To cancel the voltage offset that is otherwise caused by the input bias currents, set the parallel value of R1 and R2 equal to the parallel value of RF and RG. C must be added to limit coupling of noise into the positive input. For example, if gain of –2 V/V is required and RF = 2 kΩ, select RG = 1 kΩ to set the gain. R1 = R2 = 2 × 667 Ω = 1.33 kΩ for the mid-supply voltage bias and for op-amp input-bias current cancellation. A good value for C is 0.1 µF. The resistor divider costs less than the 2.5-V reference in Figure 71 but increases the current from the 5-V supply. Any noise or variation in the 5-V supply also comes into the circuit through this bias setup but be band-limited by the pole formed with R1 || R2 and C.
These examples are only a few of the ways to implement a single-supply design. Many other designs exist that can often be simpler if AC-coupled inputs are allowed. A good compilation of options can be found in the Single-Supply Op Amp Design Techniques application report.