SBOS673 September 2017 OPA837

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics: VS = 5 V
    6. 6.6Electrical Characteristics: VS = 3 V
    7. 6.7Typical Characteristics: VS = 5.0 V
    8. 6.8Typical Characteristics: VS = 3.0 V
    9. 6.9Typical Characteristics: ±2.5-V to ±1.5-V Split Supply
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagrams
    3. 7.3Feature Description
      1. 7.3.1OPA837 Comparison
      2. 7.3.2Input Common-Mode Voltage Range
      3. 7.3.3Output Voltage Range
      4. 7.3.4Power-Down Operation
      5. 7.3.5Low-Power Applications and the Effects of Resistor Values on Bandwidth
      6. 7.3.6Driving Capacitive Loads
    4. 7.4Device Functional Modes
      1. 7.4.1Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 7.4.2Single-Supply Operation (2.7 V to 5.4 V)
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1 Noninverting Amplifier
      2. 8.1.2 Inverting Amplifier
      3. 8.1.3 Output DC Error Calculations
      4. 8.1.4 Output Noise Calculations
      5. 8.1.5 Instrumentation Amplifier
      6. 8.1.6 Attenuators
      7. 8.1.7 Differential to Single-Ended Amplifier
      8. 8.1.8 Differential-to-Differential Amplifier
      9. 8.1.9 Pulse Application With Single-Supply Circuit
      10. 8.1.10ADC Driver Performance
    2. 8.2Typical Applications
      1. 8.2.1Active Filters
        1. 8.2.1.1Design Requirements
        2. 8.2.1.2Detailed Design Procedure
        3. 8.2.1.3Application Curves
      2. 8.2.2Implementing a 2:1 Active Multiplexer
        1. 8.2.2.1Design Requirements
        2. 8.2.2.2Detailed Design Procedure
      3. 8.2.31-Bit PGA Operation
        1. 8.2.3.1Design Requirements
        2. 8.2.3.2Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Receiving Notification of Documentation Updates
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Noninverting Amplifier

The OPA837 can be used as a noninverting amplifier with a signal input to the noninverting input, VIN+. A basic block diagram of the circuit is illustrated in Figure 61. VREF is often ground when split supplies are used.

Calculate the amplifier output according to Equation 1 if VIN = VREF + VSIG.

Equation 1. OPA837 EQ1_vout_los713.gif

The signal gain of the circuit is set by Equation 2, and VREF provides a reference around which the input and output signals swing. Output signals are in-phase with the input signals within the flat portion of the frequency response. For a high-speed, low-noise device such as the OPA837, the values selected for RF (and RG for the desired gain) can strongly influence the operation of the circuit. For the characteristic curves, the noninverting circuit of Figure 73 shows the test configuration set for a gain of 2 V/V. Table 2 lists the recommended resistor values over gain.

Equation 2. OPA837 Iline1_G_los713.gif
OPA837 sbos673_sch_Non_inverting_GainX2.gif Figure 73. Characterization Test Circuit for Network, Spectrum Analyzer

Table 2 lists the recommended resistor values from target gains of 1 V/V to 10 V/V where standard E96 values are shown. This table controls the RF and RG values to set the resistor noise contribution at approximately 50% of the total output noise power. These values increase the spot noise at the output over what the op amp voltage noise produces by 41%. Lower values reduce the output noise of any design at the cost of more power in the feedback circuit. Using the TINA model and simulation tool shows the impact of different resistor value choices on response shape and noise.

Table 2. Noninverting Recommended Resistor Values

TARGET GAIN (V/V)RF (Ω)RG (Ω)ACTUAL GAIN (V/V)GAIN (dB)
10Open1.000.00
1.5119023701.503.53
2200020002.006.02
3226011303.009.54
423707874.0112.07
524906195.0214.02
62550511 5.9915.55
726104327.0416.95
826703837.97 18.03
9 2670332 9.04 19.13
102670 294 10.0820.07

Inverting Amplifier

The OPA837 can be used as an inverting amplifier with a signal input to the inverting input, VIN–, through the gain-setting resistor RG. A basic block diagram of the circuit is illustrated in Figure 62.

The output of the amplifier can be calculated according to Equation 3 if VIN = VREF + VSIG and the noninverting input is biased to VREF.

Equation 3. OPA837 EQ2_vout2_los713.gif

The signal gain of the circuit is set by Equation 4 and VREF provides a reference point around which the input and output signals swing. For bipolar-supply operation, VREF is often ground. The output signal is 180˚ out-of-phase with the input signal in the pass band of the application. Figure 74 shows the 50-Ω input matched configuration used for the inverting characterization plots set up for a gain of –1 V/V. In this case, an added termination resistor, RT, is placed in parallel with the input RG resistor to provide an impedance match to 50-Ω test equipment. The output network appears as a 2-kΩ load but with a 50-Ω source to the network analyzer. This output interface network does add a 37.9-dB insertion loss that is normalized out in the characterization curves. Table 3 lists the suggested values for RF, RG, and RT for inverting gains from –0.5 V/V to –10 V/V. If a 50-Ω input match is not required, eliminate the RT element.

Equation 4. OPA837 Iline2_G2_los713.gif
OPA837 sbos673_sch_Inverting_GainX1.gif Figure 74. Inverting Characterization Circuit for Network Analyzer

Table 3. Inverting Recommended Resistor Values

INVERTING GAIN (V/V)RF (Ω)RG (Ω)STANDARD RT (Ω)INPUT ZI (Ω)ACTUAL (V/V)GAIN (dB)
–0.51190237051.1 50.02 –0.50 –5.98
–1 20002000 51.1 49.83–1.000.00
–22260113052.349.99 –2.006.02
–3237078753.650.18 –3.019.58
–4 249061954.950.43–4.0212.09
–52550511 54.9 49.57 –4.99 13.96
–6 261043256.249.73–6.04 15.62
–7 2670383 57.650.07 –6.97 16.87
–8 2670 3325950.10 –8.04 18.11
–9 2670 294 60.450.11–9.08 19.16
–102670 26761.950.25–10.00 20.00

Output DC Error Calculations

The OPA837 can provide excellent DC signal accuracy because of its high open-loop gain, high common-mode rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of this low input offset voltage, pay careful attention to input bias current cancellation. The low-noise input stage for the OPA837 has a relatively high input bias current (0.34 µA typical out the pins) but with a close match between the two input currents. The OPA837 is a negative rail input device using PNP input devices where the base current flows out of the device pins. A large resistor to ground on the V+ input shifts the pin voltage positively because of the input bias current. The mismatch between the two input bias currents is very low, typically only ±10 nA of input offset current. Match the DC source impedances out of the two inputs to reduce the total output offset voltage. Figure 66 illustrates an example of resistor matching for bias current cancellation. Analyzing the simple circuit of Figure 66 (using a gain of 2-V/V target with RF = RG = 2 kΩ) illustrates that the noise gain for the input offset voltage drift is 1 + 2 kΩ / 2 kΩ = 2 V/V. This value results in an output drift term of ±1.6 µV/°C × 2 = ±3.2 µV/°C (DCK package). Because the two impedances out of the inputs are matched, the residual error from the maximum ±250 pA/°C offset current drift is this maximum IOS drift times the 2-kΩ feedback resistor value, or ±50 µV/°C. The total output DC error drift band is ±53.2 µV/°C. If the output DC drift is more important than reduced feedback currents, lower the resistor values to reduce the dominant drift term resulting from the IOS term.

Output Noise Calculations

The unity-gain stable, voltage-feedback OPA837 op amp offers among the lowest input voltage and current noise terms for any device with a supply current less than 0.7 mA. Figure 75 shows the op amp noise analysis model that includes all noise terms. In this model, all noise terms are shown as noise voltage or current density terms in nV/√Hz or pA/√Hz.

OPA837 ai_noise_model_sbos673.gif Figure 75. Op Amp Noise Analysis Model

The total output spot noise voltage is computed as the square root of the squared contributing terms to the output noise voltage. This computation is adding all the contributing noise powers at the output by superposition, then taking the square root to return to a spot noise voltage. The last term includes the noise for both the RG and RF resistors. Equation 5 shows the general form for this output noise voltage using the terms presented in Figure 75.

Equation 5. OPA837 eq_07_sbos303.gif

Dividing this expression by the noise gain (NG = 1 + RF / RG), as shown in Equation 6, gives the equivalent input referred spot noise voltage at the noninverting input.

Equation 6. OPA837 eq_08_sbos303.gif

Using the resistor values listed in Table 2 with RS = 0 Ω results in a constant input-referred voltage noise of < 7 nV/√Hz. Reducing the resistor values can reduce this noise value towards the 4.7 nV/√Hz intrinsic to the OPA837. As shown in Equation 5, adding the RS for bias current cancellation in noninverting mode adds the noise from the RS to the total output noise. In inverting mode, bypass the RS bias current cancellation resistor with a capacitor for the best noise performance. For more details on op amp noise analysis, see the Noise Analysis for High-Speed Op Amps application report.

Instrumentation Amplifier

Figure 76 is an instrumentation amplifier that combines the high input impedance of the differential-to-differential amplifier circuit and the common-mode rejection of the differential-to-single-ended amplifier circuit. This circuit is often used in applications where high input impedance is required (such as taps from a differential line) or in cases where the signal source is a high impedance.

The output of the amplifier can be calculated according to Equation 7 if VIN+ = VCM + VSIG+ and VIN– = VCM + VSIG–.

Equation 7. OPA837 EQ5_vout5_los713.gif

Equation 8 shows the signal gain of the circuit. The input VCM is rejected, and VREF provides a reference voltage or level shift around which the output signal swings. The single-ended output signal is in-phase to the lower input signal polarity.

Equation 8. OPA837 Iline5_G5_los713.gif
OPA837 instru_amp_sbos673.gif Figure 76. Instrumentation Amplifier (INA)

Integrated INA solutions are available, but the OPA837 device provides a high-frequency solution at relatively low power (< 1.8 mA for the three op-amp solution). For best CMRR performance, resistors must be matched. A good rule of thumb is CMRR ≈ the resistor tolerance; so a 0.1% tolerance provides approximately 60-dB CMRR. For higher gain INA implementations with higher bandwidths, apply the OPA838 to the circuit of Figure 76.

Attenuators

The noninverting circuit of Figure 61 has a minimum gain of 1. To implement attenuation, a resistor divider can be placed in series with the positive input, and the amplifier set for a gain of 1 V/V by shorting VOUT to VIN– and removing RG. Because the op amp input is high impedance, the resistor divider sets the attenuation.

The inverting circuit of Figure 62 is used as an attenuator by making RG larger than RF. The attenuation is the resistor ratio. For example, a 10:1 attenuator can be implemented with RF = 2 kΩ and RG = 20 kΩ.

Differential to Single-Ended Amplifier

Figure 77 shows a differential amplifier that converts differential signals to single-ended in a single stage and provides gain (or attenuation) and level shifting. This circuit can be used in applications such as a line receiver for converting a differential signal from a Cat5 cable to a single-ended output signal.

The output of the amplifier can be calculated according to Equation 9 if VIN+ = VCM + VSIG+ and VIN– = VCM + VSIG–.

Equation 9. OPA837 EQ3_vout3_los713.gif

The signal gain of the circuit is shown in Equation 10, VCM is rejected, and VREF provides a level shift or reference voltage around which the output signal swings. The single-ended output signal is in-phase with the noninverting input signal. VREF is often ground when split supplies are used on the op amp.

Equation 10. OPA837 Iline3_G3_los713.gif
OPA837 dif_sng_amp_sbos673.gif Figure 77. Differential to Single-Ended Amplifier

Line termination can be accomplished by adding a shunt resistor across the VIN+ and VIN– inputs. The differential impedance is the shunt resistance in parallel with the input impedance of the amplifier circuit, which is usually much higher. For low gain and low line impedance, the resistor value to add is approximately the impedance of the line. For example, if a 100-Ω Cat5 cable is used with a gain of 1 V/V amplifier and RF = RG = 2 kΩ, adding a 100-Ω shunt across the input gives a differential impedance of 99 Ω, which is an adequate match for most applications.

For best CMRR performance, resistors must be matched. Assuming CMRR ≈ the resistor tolerance, a 0.1% tolerance provides approximately 60-dB CMRR.

Differential-to-Differential Amplifier

Figure 78 shows a differential amplifier that is used to amplify differential signals to a differential output. This circuit has high input impedance and is used in differential line driver applications where the signal source is a high-impedance driver (for example, a differential DAC) that must drive a line.

The output of the amplifier can be calculated according to Equation 11 if VIN± is set to VCM + VSIG±.

Equation 11. OPA837 EQ4_vout4_los713.gif

The signal gain of the circuit is shown in Equation 12, and VCM passes with unity gain. The amplifier combines two noninverting amplifiers into one differential amplifier that shares the RG resistor, which makes RG effectively half its value when calculating the gain. The output signals are in-phase with the input signals.

Equation 12. OPA837 Iline4_G4_los713.gif
OPA837 dif_dif_amp_sbos673.gif Figure 78. Differential-to-Differential Amplifier

Pulse Application With Single-Supply Circuit

For pulsed applications where the signal is at ground and pulses to a positive or negative voltage, the circuit bias-voltage considerations differ from those in an application with a signal that swings symmetrically around a reference point. Figure 79 shows a circuit where the signal is at ground (0 V) and pulses to a positive value. The waveforms are shown slightly above ground because the output stage requires approximately 100 mV headroom to the supplies. To operate with the I/O swing truly to ground on a single-supply setup, consider using the fixed –0.23-V output LM7705.

OPA837 Ninv_sply_pulse_sbos673.gif Figure 79. Noninverting Single-Supply Circuit With Pulse

As shown in Figure 80, an inverting amplifier is more appropriate if the input signal pulses negative from ground. A key consideration in noninverting and inverting cases is that the input and output voltages are kept within the limits of the amplifier. Because the VICR of the OPA837 includes the negative supply rail, the OPA837 op amp is well-suited for this application.

OPA837 inv_sply_pulse_sbos673.gif Figure 80. Inverting Single-Supply Circuit With Pulse

ADC Driver Performance

The OPA837 provides excellent performance when driving high-performance delta-sigma (ΔΣ) or successive-approximation-register (SAR) ADCs in low-power audio and industrial applications.

Figure 81 repeats the front page diagram. Many designs prefer to work with a true 0-V input range to 0-V output at the ADC. The 100-mV output headroom requirement for the OPA837 then requires a small negative supply to hold the output linearity to ground. This supply is provided in this example using the low-cost LM7705 fixed negative, –0.23-V output regulator. On a 5-V supply, the input headroom requires at least a 1.2-V headroom to that supply. As shown in Figure 81, this requirement limits the maximum input to 3.8 V. The SAR operates with a precision 4.096-V reference provided by the REF5040, where the gain of 1.05 V/V takes the 3.8-V maximum input to a 4.0-V maximum output. The RC values have been set to limit the overshoot at the OPA837 output pin to reduce clipping on fast (50 ns) transitions.

OPA837 OPA837-front-page-diagram-sbos673.gif Figure 81. OPA837 and ADS8860 Example Circuit

Typical Applications

Active Filters

The OPA837 is a good choices for active filters. Figure 83 and Figure 82 show MFB and Sallen-Key circuits designed implementing second-order low-pass Butterworth filter circuits. Figure 84 shows the frequency response.

The main difference is that the MFB active filter provides an inverting amplifier in the pass band and the Sallen-Key active filter is noninverting. The primary advantage for each active filter is that the Sallen-Key filter in unity gain has no resistor gain error term or feedback resistor noise contribution. The MFB active filter has better attenuation properties beyond the bandwidth of the op amp. The example circuits are assuming a split-supply operation but single-supply operation is possible with midscale biasing.

OPA837 MFB_cir_sbos673.gif Figure 82. MFB Active Filter, 100-kHz, Second-Order, Low-Pass Butterworth Filter Circuit
OPA837 sllen_key_sbos673.gif Figure 83. Sallen-Key Active Filter, 100-kHz, Second-Order, Low-Pass Butterworth Filter Circuit

Design Requirements

For both designs, target the following filter shape characteristic:

  • Gain of 1 V/V
  • 100-kHz Butterworth response
  • Q = 0.707 gives a flat Butterworth design

Scale the resistors down to reduce their noise contribution. In the MFB design, the input resistor is the in-band load to the prior stage. Use values slightly below the gain of –1 V/V in Table 3. The Sallen-Key filter shows a high impedance input in-band, so scale those resistors down further to improve noise.

The output DC error and drift can be improved by adding bias current cancellation resistors. For the MFB filter that is a resistor (and a noise filter capacitor) on the noninverting input to ground equal to the resistor inside the loop times the noise gain. For the Sallen-Key design, add a feedback resistor equal to the sum of the two input resistors.

Detailed Design Procedure

The filter designs shown in this section used an improved design flow that reduces the resistor noise and noise gain peaking. For the MFB filter, the design was based on the information in the Design Methodology for MFB Filters in ADC Interface Applications application note.

For the Sallen-Key design, the solution is based on the information in the Component Pre-Distortion for Sallen Key Filters application note.

Application Curves

Figure 84 shows the comparative response curves for each of the filter design examples. Both filters hit the desired response shape exactly. However, notice the loss of stop-band rejection in the Sallen-Key design. This loss results from the op amp output impedance increasing at higher frequencies and allowing the signal to feed through the feedback capacitor to the output.

Figure 84 shows a comparison of the output spot noise for the two designs. The Sallen-Key is much lower due to the lower resistor values used. Also, the MFB shows a noise gain of 2V/V vs the Sallen-Key gain of 1V/V. This immediately increases the MFB output noise by at least 2X the input voltage noise from the op amp. Then the higher resistor values also increase the total output noise for the MFB.

OPA837 D083_SBOS673_MFB-and-SKF-SSBW-response.gif
Figure 84. MFB and Sallen-Key Active Filters, Second-Order, Low-Pass Butterworth Filter Response
OPA837 D084_SBOS673_MFB-and-SKF-noise.gif
Figure 85. Output Spot Noise Comparison

Implementing a 2:1 Active Multiplexer

The OPA837 includes a unique feature that enables a much improved wired-or mux operation. When disabled, an internal switch opens from the inverting input to the active transistors isolating those nonlinear loads from the signal being driven back into the inverting input through the active channel. Figure 86 illustrates a simple example of this multiplexer. In this figure, one of two signals are selected to be passed on to a shared output. The logic control turns both amplifiers off (logic low) prior to turning one of them on. This control eliminates both outputs being active at the same time. If both amplifiers must be on, as in the simple switch illustrated in Figure 86, adding 100-Ω isolating resistors inside the loop at the outputs limits the current flow when both amplifiers are turned on. This solution offers a very high input impedance to both inputs, very low buffered output drive, and nearly perfect channel-to-channel isolation. The example of Figure 86 also includes a –0.23-V supply generator to allow true swing to ground on the output pins. This negative supply generator is optional if the outputs are more than 0.1 V above ground or intended to be AC-coupled. Testing with a single channel active and an off channel attached to the output showed no degradation in harmonic distortion; see Figure 17 and Figure 35. This approach can be expanded to more than two channels or to operate with gain in the channels. Adding more than two select channels in parallel should add 100-Ω feedback resistors to isolate the inverting input capacitance from the active output channel.

OPA837 sbos673_sch_ActiveMUX.gif Figure 86. 2:1 Active Multiplexer

Design Requirements

To implement a 2:1 active mux, connect the outputs of two OPA837 devices together with separate input signals. If termination is required for the input signals, add this termination as a resistor to ground on the noninverting inputs. The inputs accept an input range from 0 V to 3.8 V by using a negative 0.23-V supply generator, such as the LM7705.

Detailed Design Procedure

Aside from simply connecting the two outputs together as shown in Figure 86, there are several other considerations as well:

  • If the source impedance is not 0 Ω, consider adding a resistor in the feedback networks equal to that source impedance to reduce the output DC error resulting from bias currents
  • If the logic control can place both channels on at the same time, place 100-Ω resistors inside the feedback loop to limit supply currents when both outputs are active
  • If a matched gain is desired for the two inputs, configure the op amps for that gain instead of gain of 1 V/V
  • If the load is capacitive, add the required ROUT before the summing point on each op amp output

1-Bit PGA Operation

Using the internal inverting input switch that operates along with the power disable function can also allow a simple gain selection on a single input signal. Figure 87 shows an example gain select of either 1 V/V or 2 V/V from a single input to a single output. The logic disables both channels before turning one of them on to avoid high currents in both outputs to be active at the same time. If this approach is not possible, as in the simple switch shown in Figure 87, insert 100-Ω resistors inside the loop of each op amp output. A bipolar supply is shown in Figure 87, but any of the single-supply options are also possible. Any combination of gains can be implemented, but wide gain ranges show a larger change in signal bandwidth. This approach can be expanded to more than two gain settings. Testing with the circuit of Figure 87 showed no change in harmonic distortion; see Figure 18 and Figure 36.

OPA837 sbos673_sch_1-BitPGA.gif Figure 87. 1-Bit PGA

Design Requirements

Configure two OPA837 device outputs in different gains when driving the noninverting input with the same input signal. Select one the two channels using the disable control. Set one channel to a gain of 1 V/V and the second channel to a gain of 2 V/V using the recommended 2-kΩ values from Table 2.

Detailed Design Procedure

The simple design of Figure 87 has several options and details to consider, which include:

  • For split-supply operation, the disable control line must operate to within 0.55 V of the negative supply to disable a channel. A logic level shift is required.
  • Any combination of gains can be implemented. However, the signal bandwidths may vary widely through the gain bandwidth product effect between the two channels if the gains are widely separated. If a more constant bandwidth between gains is desired, consider adding a fixed RC filter after the combined outputs at a lower cutoff frequency than the slowest gain setting.