ZHCSGK6 July   2017 ONET2804TLP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 DC Electrical Characteristics
    5. 6.5 AC Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics: General
    8. 6.8 Typical Characteristics: Eye Diagrams
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Signal Path
      2. 7.3.2 Gain Adjustment
      3. 7.3.3 Amplitude Adjustment
      4. 7.3.4 Rate Select
      5. 7.3.5 Threshold Adjustment
      6. 7.3.6 Filter Circuitry
      7. 7.3.7 AGC and RSSI
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pad Control
      2. 7.4.2 Two-Wire Interface Control
    5. 7.5 Programming
      1. 7.5.1 Bus Idle
      2. 7.5.2 Start Data Transfer
      3. 7.5.3 Stop Data Transfer
      4. 7.5.4 Data Transfer
      5. 7.5.5 Acknowledge
    6. 7.6 Register Maps
      1. 7.6.1  Register Descriptions
      2. 7.6.2  Register 0: Control Settings (address = 00h) [reset = 0h]
      3. 7.6.3  Register 1: Amplitude and Rate for Channel 1 (address = 01h) [reset = 0h]
      4. 7.6.4  Register 2: Threshold and Gain for Channel 1 (address = 02h) [reset = 0h]
      5. 7.6.5  Register 7: Amplitude and Rate for Channel 2 (address = 07h) [reset = 0h]
      6. 7.6.6  Register 8: Threshold and Gain for Channel 1 (address = 08h) [reset = 0h]
      7. 7.6.7  Register 13: Amplitude and Rate for Channel 3 (address = 0Dh) [reset = 0h]
      8. 7.6.8  Register 14: Threshold and Gain for Channel 3 (address = 0Eh) [reset = 0h]
      9. 7.6.9  Register 19: Amplitude and Rate for Channel 4 (address = 13h) [reset = 0h]
      10. 7.6.10 Register 20: Threshold and Gain for Channel 4 (address = 14h) [reset = 0h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Pad Control Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Two-Wire Control Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

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7 Detailed Description

7.1 Overview

The Functional Block Diagram section shows a simplified block diagram for one channel of the ONET2804TLP.

The ONET2804TLP consists of the signal path, supply filters, a control block for dc input bias, automatic gain control (AGC) and received signal strength indication (RSSI), an analog reference block and a two-wire serial interface and control logic block.

The signal path consists of a transimpedance amplifier (TIA) stage, a voltage amplifier, and a current-mode logic (CML) output buffer. The on-chip filter circuit provides a filtered VCC for the PIN photodiode and for the transimpedance amplifier. The RSSI provides the bias for the TIA stage and control for the AGC.

The DC input bias circuit and automatic gain control use internal low-pass filters to cancel the DC current on the input and to adjust the transimpedance amplifier gain. Furthermore, circuitry is provided to monitor the received signal strength.

The output amplitude, gain, bandwidth, and input threshold can be globally controlled through pin settings or each channel can be individually controlled through the two-wire interface.

7.2 Functional Block Diagram

ONET2804TLP sbas796_fbd.gif

7.3 Feature Description

7.3.1 Signal Path

The first stage of the signal path is a transimpedance amplifier that converts the photodiode current into a voltage. If the input signal current exceeds a certain value, the transimpedance gain is reduced by means of a nonlinear AGC circuit to limit the signal amplitude.

The second stage is a limiting voltage amplifier that provides additional limiting gain and converts the single-ended input voltage into a differential data signal. The output stage provides CML outputs with an on-chip, 50-Ω termination to VCC.

The TIA has adjustable gain, amplitude, bandwidth, and input threshold that can be globally controlled through pad settings or each channel can be individually controlled through the two-wire interface. The default mode of operation is pad control where the state (open, high, or low) of the AMPL, BW, GAIN, and TRSH pads sets the respective parameter. To enable two-wire control, set the I2CENA pad high and the functionality of each channel can be controlled individually through the two-wire interface.

7.3.2 Gain Adjustment

The gain of all TIAs can be adjusted using the GAIN pad (pad 8) in pad control mode. Gain is set to default if the pad is left open. Gain is reduced by approximately 4 dB if the pad is tied to ground, and reduced by approximately 8 dB if the pad is tied to VCC. In two-wire control mode, the gain of each channel can be adjusted from minimum to default. Gain is controlled with the GAIN[1:0] bits in registers 2, 8, 14, and 20 for channels 1, 2, 3, and 4, respectively.

7.3.3 Amplitude Adjustment

The output amplifier of all buffers can be adjusted using the AMPL pad (pad 6) in pad control mode. The amplitude is set to 300 mVPP differential if the pad is left open, 250 mVPP if the pad is tied to ground, and 450 mVPP if the pad is tied to VCC voltage (recommended mode of operation). In two-wire control mode, the amplitude of each channel can be adjusted from 0 mVPP to 600 mVPP. The amplitude is controlled with the AMPL[3:0] bits in registers 1, 7, 13, and 19 for channels 1, 2, 3, and 4, respectively.

7.3.4 Rate Select

The small-signal bandwidth can be adjusted using the RATE pad (pad 7) in pad control mode. Bandwidth is typically 20 GHz if the pad is left open. Bandwidth is reduced by approximately 0.4 GHz if the pad is tied to ground, and increased by approximately 0.4 GHz if the pad is tied to VCC. In two-wire control mode, the bandwidth of each channel can be adjusted up or down using the RATE[3:0] register settings in registers 1, 7, 13, and 19 for channels 1, 2, 3, and 4, respectively.

7.3.5 Threshold Adjustment

The TIAs have DC offset cancellation to maintain a 50% crossing point; however, the crossing point can be adjusted using the TRSH pad (pad 41) in pad control mode. No threshold adjustment is applied if the pad is left open. The crossing point is shifted up approximately 12% if the pad is tied to ground, and is shifted down by approximately 12% if the pad is tied to VCC. In two-wire control mode, the crossing point can be adjusted up or down using the TH[3:0] register settings in registers 2, 8, 14, and 20 for channels 1, 2, 3, and 4, respectively.

7.3.6 Filter Circuitry

The FILTERx pins provide a regulated and filtered VCC for a PIN photodiode bias. The supply voltages for the transimpedance amplifier have on-chip capacitors but external filter capacitors are recommended to be used as well for best performance. The input stage has a separate VCC supply (VCCIx) that is not connected on-chip to the supply of the limiting and CML stages (VCCOx).

7.3.7 AGC and RSSI

The voltage drop across the regulated photodiode FET is monitored by the bias and RSSI control circuit block in the case where a PIN diode is biased using the FILTERx pins.

If the DC input current exceeds a certain level then this current is partially cancelled by means of a controlled current source. This cancellation keeps the transimpedance amplifier stage within sufficient operating limits for optimum performance.

The automatic gain control circuitry adjusts the voltage gain of the AGC amplifier to ensure limiting behavior of the complete amplifier.

Finally, this circuit block senses the current through the FILTERx FET and generates a mirrored current that is proportional to the input signal strength. The mirrored currents are available at the RSSIx outputs and can be sunk to ground (GND) using an external resistor. For proper operation, ensure that the voltage at the RSSIx pad does not exceed VCC – 0.65 V.

7.4 Device Functional Modes

The device has two functional modes of operation: pad control mode and two-wire interface control mode.

7.4.1 Pad Control

The default mode of operation is pad control and the amplitude is recommended to be increased to the 450 mVPP setting by bonding AMPL (pad 6) to VCC. If further adjustment is desired as described previously, then the RATE (pad 7), GAIN (pad 8), and TRSH (pad 41) control pads and can be bonded to either ground (GND) or VCC.

7.4.2 Two-Wire Interface Control

To enable two-wire interface, the I2CENA (pad 5) control pad must be bonded to VCC. In this mode of operation, pad control is not functional and all control is initiated through the two-wire interface as described in the Programming section.

7.5 Programming

The ONET2804TLP uses a two-wire serial interface for digital control. For example, the two circuit inputs (SDA and SCK) are driven by the serial data and serial clock from a microcontroller. Both inputs include 10-kΩ pullup resistors to VCC. For driving these inputs, an open-drain output is recommended. The two-wire interface allows write access to the internal memory map to modify control registers and read access to read out control and status signals. The ONET2804TLP is a slave device only, which means that the device cannot initiate a transmission, but always relies on the availability of the SCK signal for the duration of the transmission. The master device provides the clock signal as well as the START and STOP commands. The device is recommended to be used on a bus with only one master. The protocol for a data transmission is as follows:

  1. START command
  2. 7-bit slave address (0001100) followed by an eighth bit that is the data direction bit (R/W). A zero indicates a write operation and a 1 indicates a read operation.
  3. 8-bit register address
  4. 8-bit register data word
  5. STOP command

Regarding timing, the ONET2804TLP is I2C compatible. Figure 13 illustrates the typical timing and Figure 14 illustrates a complete data transfer. Parameters for Figure 13 are defined in the Timing Requirements table.

ONET2804TLP sbas796_timing_diagram.gif Figure 13. I2C Timing Diagram
ONET2804TLP sbas796_data_transfer.gif Figure 14. Data Transfer

7.5.1 Bus Idle

Both the SDA and SCK lines remain high.

7.5.2 Start Data Transfer

A change in the state of the SDA line from high to low when the SCK line is high defines a START condition (S). Each data transfer is initiated with a START condition.

7.5.3 Stop Data Transfer

A change in the state of the SDA line from low to high when the SCK line is high defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, to continue communication on the bus, the master can generate a repeated START condition and address another slave without first generating a STOP condition.

7.5.4 Data Transfer

Only one data byte can be transferred between a START and a STOP condition. The receiver acknowledges the transfer of data.

7.5.5 Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver does not acknowledge the slave address, the data line must be left high by the slave. The master can then generate a STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more data bytes, the master must abort the transfer. This requirement is indicated by the slave generating a not acknowledge on the first subsequent byte. The slave leaves the data line high and the master generates the STOP condition.

7.6 Register Maps

Table 1 lists the registers for the ONET2804TLP.

Table 1. Register Map

REGISTER REGISTER DATA
NAME ADDRESS 7 6 5 4 3 2 1 0
Register 0 00h RESET PD RESERVED RESERVED RESERVED RESERVED RESERVED PWRITE
Register 1 01h RATE3 RATE2 RATE1 RATE0 AMP3 AMP2 AMP1 AMP0
Register 2 02h PD DIS GAIN1 GAIN0 TH3 TH2 TH1 TH0
Register 3 03h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 4 04h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 5 05h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 6 06h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 7 07h RATE3 RATE2 RATE1 RATE0 AMP3 AMP2 AMP1 AMP0
Register 8 08h PD DIS GAIN1 GAIN0 TH3 TH2 TH1 TH0
Register 9 09h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 10 0Ah RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 11 0Bh RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 12 0Ch RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 13 0Dh RATE3 RATE2 RATE1 RATE0 AMP3 AMP2 AMP1 AMP0
Register 14 0Eh PD DIS GAIN1 GAIN0 TH3 TH2 TH1 TH0
Register 15 0Fh RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 16 10h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 17 11h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 18 12h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 19 13h RATE3 RATE2 RATE1 RATE0 AMP3 AMP2 AMP1 AMP0
Register 20 14h PD DIS GAIN1 GAIN0 TH3 TH2 TH1 TH0
Register 21 15h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 22 16h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 23 17h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 24 18h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Register 25 19h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

7.6.1 Register Descriptions

This section describes the circuit functionality based on the register settings. Table 2 defines the various register bit field types used in this document.

Table 2. Register Bit Field Types

SYMBOL DESCRIPTION ACCESS, READ ACTION, WRITE VALUE
R Read Read-only
R/W Read, write, or both Read-write
W Write Write-only

7.6.2 Register 0: Control Settings (address = 00h) [reset = 0h]

Figure 15. Register 0
7 6 5 4 3 2 1 0
RESET PD RESERVED RESERVED RESERVED RESERVED RESERVED PWRITE
W-0h R/W-0h R-Xh R-Xh R-Xh R-Xh R-Xh R/W-0h

Table 3. Register 0 Field Descriptions

Bit Field Type Reset Description
7 RESET W 0h Reset registers bit.
1 = Resets all registers to default values
0 = Normal operation
6 PD R/W 0h Power-down bit.
1 = Power down all channels (ICC is approximately 4 mA)
0 = Normal operation
5-1 Reserved R Undefined Reserved. Read-only.
0 PWRITE R/W 0h Parallel write mode bit.
1 = Parallel write enabled (write register value to all channels)
0 = Serial write

7.6.3 Register 1: Amplitude and Rate for Channel 1 (address = 01h) [reset = 0h]

Figure 16. Register 1
7 6 5 4 3 2 1 0
RATE3 RATE2 RATE1 RATE0 AMP3 AMP2 AMP1 AMP0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 4. Register 1 Field Descriptions

Bit Field Type Reset Description
7-4 RATE[3 :0] R/W 0h Rate adjustments bits for channel 1.
0000 = 21 GHz (default)
0111 = BW decrease of approximately 0.4 GHz
1111 = BW increase of approximately 0.4 GHz
All others: Do not use
3-0 AMP[3:0] R/W 0h Amplitude adjustment bits for channel 1.
Table 5 lists the bit settings for AMP[3:0].

Table 5. AMP[3:0] Bit Settings

BITS AMPLITUDE ADJUSTMENT (mVPP) BITS AMPLITUDE ADJUSTMENT (mVPP)
0000 0 (default) 1000 250
0001 50 1001 300
0010 100 1010 350
0011 150 1011 400
0100 200 1100 450
0101 250 1101 500
0110 300 1110 550
0111 350 1111 600

7.6.4 Register 2: Threshold and Gain for Channel 1 (address = 02h) [reset = 0h]

Figure 17. Register 2
7 6 5 4 3 2 1 0
PD DIS GAIN1 GAIN0 TH3 TH2 TH1 TH0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 6. Register 2 Field Descriptions

Bit Field Type Reset Description
7 PD R/W 0h Power-down bit for channel 1.
1 = Power down channel 1
0 = Normal operation
6 DIS R/W 0h Disable output buffer for channel 1.
1 = Disable channel 1 output buffer
0 = Normal operation
5-4 GAIN[1:0] R/W 0h Gain adjustment bits for channel 1.
00 = Default
01 = Do not use
10 = Medium (–4 dB)
11 = Minimum (–8 dB)
3-0 TH[3:0] R/W 0h Threshold adjustment bits for channel 1.
0000 = Zero shift
0001 = Minimum positive shift
0111 = Maximum positive shift
1000 = Zero shift
1001 = Minimum negative shift
1111 = Maximum negative shift

7.6.5 Register 7: Amplitude and Rate for Channel 2 (address = 07h) [reset = 0h]

Figure 18. Register 7
7 6 5 4 3 2 1 0
RATE3 RATE2 RATE1 RATE0 AMP3 AMP2 AMP1 AMP0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7. Register 7 Field Descriptions

Bit Field Type Reset Description
7-4 RATE[3:0] R/W 0h Rate adjustments bits for channel 2.
0000 = 21 GHz (default)
0111 = BW decreases by approximately 0.4 GHz
1111 = BW increases by approximately 0.4 GHz
3-0 AMP[3:0] R/W 0h Amplitude adjustment bits for channel 2.
Table 5 lists the bit settings for AMP[3:0].

7.6.6 Register 8: Threshold and Gain for Channel 1 (address = 08h) [reset = 0h]

Figure 19. Register 8
7 6 5 4 3 2 1 0
PD DIS GAIN1 GAIN0 TH3 TH2 TH1 TH0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8. Register 8 Field Descriptions

Bit Field Type Reset Description
7 PD R/W 0h Power-down bit for channel 2.
1 = Power down channel 2
0 = Normal operation
6 DIS R/W 0h Disable output buffer for channel 2.
1 = Disable channel 2 output buffer
0 = Normal operation
5-4 GAIN[1:0] R/W 0h Gain adjustment bits for channel 2.
00 = Default
01 = Do not use
10 = Medium (–4 dB)
11 = Minimum (–8 dB)
3-0 TH[3:0] R/W 0h Threshold adjustment bits for channel 2.
0000 = Zero shift
0001 = Minimum positive shift
0111 = Maximum positive shift
1000 = Zero shift
1001 = Minimum negative shift
1111 = Maximum negative shift

7.6.7 Register 13: Amplitude and Rate for Channel 3 (address = 0Dh) [reset = 0h]

Figure 20. Register 13
7 6 5 4 3 2 1 0
RATE3 RATE2 RATE1 RATE0 AMP3 AMP2 AMP1 AMP0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9. Register 13 Field Descriptions

Bit Field Type Reset Description
7-4 RATE[3:0] R/W 0h Rate adjustments bits for channel 3.
0000 = 21 GHz (default)
0111 = BW decreases by approximately 0.4 GHz
1111 = BW increases by approximately 0.4 GHz
3-0 AMP[3:0] R/W 0h Amplitude adjustment bits for channel 3.
Table 5 lists the bit settings for AMP[3:0].

7.6.8 Register 14: Threshold and Gain for Channel 3 (address = 0Eh) [reset = 0h]

Figure 21. Register 14
7 6 5 4 3 2 1 0
PD DIS GAIN1 GAIN0 TH3 TH2 TH1 TH0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10. Register 14 Field Descriptions

Bit Field Type Reset Description
7 PD R/W 0h Power-down bit for channel 3.
1 = Power down channel 3
0 = Normal operation
6 DIS R/W 0h Disable output buffer for channel 3.
1 = Disable channel 3 output buffer
0 = Normal operation
5-4 GAIN[1:0] R/W 0h Gain adjustment bits for channel 3.
00 = Default
01 = Do not use
10 = Medium (–4 dB)
11 = Minimum (–8 dB)
3-0 TH[3:0] R/W 0h Threshold adjustment bits for channel 3.
0000 = Zero shift
0001 = Minimum positive shift
0111 = Maximum positive shift
1000 = Zero shift
1001 = Minimum negative shift
1111 = Maximum negative shift

7.6.9 Register 19: Amplitude and Rate for Channel 4 (address = 13h) [reset = 0h]

Figure 22. Register 19
7 6 5 4 3 2 1 0
RATE3 RATE2 RATE1 RATE0 AMP3 AMP2 AMP1 AMP0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 11. Register 19 Field Descriptions

Bit Field Type Reset Description
7-4 RATE[3:0] R/W 0h Rate adjustments bits for channel 4.
0000 = 21 GHz (default)
0111 = BW decreases by approximately 0.4 GHz
1111 = BW increases by approximately 0.4 GHz
3-0 AMP[3:0] R/W 0h Amplitude adjustment bits for channel 4.
Table 5 lists the bit settings for AMP[3:0].

7.6.10 Register 20: Threshold and Gain for Channel 4 (address = 14h) [reset = 0h]

Figure 23. Register 20
7 6 5 4 3 2 1 0
PD DIS GAIN1 GAIN0 TH3 TH2 TH1 TH0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 12. Register 20 Field Descriptions

Bit Field Type Reset Description
7 PD R/W 0h Power-down bit for channel 4.
1 = Power down channel 4
0 = Normal operation
6 DIS R/W 0h Disable output buffer for channel 4.
1 = Disable channel 4 output buffer
0 = Normal operation
5-4 GAIN[1:0] R/W 0h Gain adjustment bits for channel 4.
00 = Default
01 = Do not use
10 = Medium (–4 dB)
11 = Minimum (–8 dB)
3-0 TH[3:0] R/W 0h Threshold adjustment bits for channel 4.
0000 = Zero shift
0001 = Minimum positive shift
0111 = Maximum positive shift
1000 = Zero shift
1001 = Minimum negative shift
1111 = Maximum negative shift