SLAS697E Data sheet | 德州仪器 TI.com.cn

SLAS697E March 2010 – November 2016 MSP430F2619S-HT

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4 Specifications

4.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
	Voltage applied at V_CC to V_SS	–0.3	4.1	V
	Voltage applied to any pin⁽²⁾	–0.3	V_CC + 0.3	V
	Diode current at any device terminal	–2	2	mA
T_stg	Storage temperature (unprogrammed device⁽³⁾)	–55	150	°C
T_stg	Storage temperature (programmed device⁽³⁾)	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, V_FB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

4.2 ESD Ratings

				MAX		UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾		±4000		V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JESD22-C101⁽²⁾		±750		V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions⁽¹⁾⁽³⁾

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage during program execution	AV_CC = DV_CC = V_CC⁽²⁾	1.8		3.6	V
V_CC	Supply voltage during flash memory programming	AV_CC = DV_CC = V_CC⁽²⁾	2.2		3.6	V
V_SS	Supply voltage	AV_SS = DV_SS = V_SS		0		V
T_A	Operating free-air temperature range		–55		150	°C
	Processor frequency ƒ_SYSTEM (Maximum MCLK frequency)⁽¹⁾⁽³⁾ (see Figure 4-1)	V_CC = 2.2 V, duty cycle = 50% ±10%	DC		10	MHz
		V_CC = 2.7 V, duty cycle = 50% ±10%	DC		12
		V_CC ≥ 3.3 V, duty cycle = 50% ±10%	DC		16

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.

(2) It is recommended to power AV_CC and DV_CC from the same source. A maximum difference of 0.3 V between AV_CC and DV_CC can be tolerated during power-up.

(3) Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.

NOTE:

Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V_CC of 2.2 V.

Figure 4-1 Operating Area

1. Wirebond Life = Time at temperature with or without bias.

2. Electromigration Fail Mode = Time at temperature with bias.

3. Silicon operating life design goal is 10 years at 105˚C junction temperature (does not include package interconnect life).

4. The predicted operating lifetime vs. junction temperature is based on reliability modeling and available qualification data.

Figure 4-2 Device Life Curve

4.4 Thermal Information

THERMAL METRIC⁽¹⁾		MSP430F2619S-HT	UNIT
		PM (QFP)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	48.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	9.9	°C/W
R_θJB	Junction-to-board thermal resistance	22.4	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	21.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

4.5 Active-Mode Supply Current Into AV_CC Excluding External Current –
Electrical Characteristics⁽¹⁾⁽²⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
I_{AM, 1MHz}	Active-mode (AM) current (1 MHz)	ƒ_DCO = ƒ_MCLK = ƒ_SMCLK = 1 MHz, ƒ_ACLK = 32,768 Hz, Program executes in flash, BCSCTL1 = CALBC1_1 MHZ, DCOCTL = CALDCO_1 MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0	T_A = –55°C to 85°C, V_CC = 2.2 V	365	395	μA
			T_A = 105°C, V_CC = 2.2 V	375	420
			T_A = 150°C, V_CC = 2.2 V	640
			T_A = –55°C to 85°C, V_CC = 3 V	515	560
			T_A = 105°C, V_CC = 3 V	525	595
			T_A = 150°C, V_CC = 3 V	700
I_{AM, 1MHz}	Active-mode (AM) current (1 MHz)	ƒ_DCO = ƒ_MCLK = ƒ_SMCLK = 1 MHz, ƒ_ACLK = 32,768 Hz, Program executes in RAM, BCSCTL1 = CALBC1_1 MHZ, DCOCTL = CALDCO_1 MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0	T_A = –55°C to 85°C, V_CC = 2.2 V	330	370	μA
			T_A = 105°C, V_CC = 2.2 V	340	390
			T_A = 150°C, V_CC = 2.2 V	660
			T_A = –55°C to 85°C, V_CC = 3 V	460	495
			T_A = 105°C, V_CC = 3 V	470	520
			T_A = 150°C, V_CC = 3 V	710
I_{AM, 4kHz}	Active-mode (AM) current (4 kHz)	ƒ_MCLK = ƒ_SMCLK = ƒ_ACLK = 32,768 Hz/8 = 4,096 Hz, ƒ_DCO = 0 Hz, Program executes in flash, SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0	T_A = –55°C to 85°C, V_CC = 2.2 V	2.1	9	μA
			T_A = 105°C, V_CC = 2.2 V	15	31
			T_A = –55°C to 85°C, V_CC = 3 V	3	11
			T_A = 105°C, V_CC = 3 V	19	32
I_{AM, 100kHz}	Active-mode (AM) current (100 kHz)	ƒ_MCLK = ƒ_SMCLK = ƒ_{DCO(0, 0)} ≉ 100 kHz, ƒ_ACLK = 0 Hz, Program executes in flash, RSELx = 0, DCOx = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 1	T_A = –55°C to 85°C, V_CC = 2.2 V	67	86	μA
			T_A = 105°C, V_CC = 2.2 V	80	99
			T_A = 150°C, V_CC = 2.2 V	190
			T_A = –55°C to 85°C, V_CC = 3 V	84	107
			T_A = 105°C, V_CC = 3 V	99	128
			T_A = 150°C, V_CC = 3 V	240

(1) All inputs are tied to 0 V or V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.

4.6 Typical Characteristics – Active-Mode Supply Current (Into DV_CC+ AV_CC)

Figure 4-3 Active-Mode Current vs V_CC, T_A = 25°C

Figure 4-4 Active-Mode Current vs DCO Frequency

4.7 Active-Mode Current vs DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER	TEST CONDITIONS		MAX	UNIT
Active-mode current supply	ƒ_SMCLK = ƒ_DCO = 1 MHz	T_A = –55°C, V_CC = 2.2 V	0.35	mA
		T_A = –40°C, V_CC = 2.2 V	0.30
		T_A = 25°C, V_CC = 2.2 V	0.36
		T_A = 125°C, V_CC = 2.2 V	0.38
		T_A = 150°C, V_CC = 2.2 V	0.42
		T_A = –55°C, V_CC = 3 V	0.50
		T_A = –40°C, V_CC = 3 V	0.49
		T_A = 25°C, V_CC = 3 V	0.51
		T_A = 125°C, V_CC = 3 V	0.55
		T_A = 150°C, V_CC = 3 V	0.60
Active-mode current supply	ƒ_SMCLK = ƒ_DCO = 12 MHz	T_A = –55°C, V_CC = 2.2 V	3.71	mA
		T_A = –40°C, V_CC = 2.2 V	3.73
		T_A = 25°C, V_CC = 2.2 V	3.79
		T_A = 125°C, V_CC = 2.2 V	4.45
		T_A = 150°C, V_CC = 2.2 V	4.60
		T_A = –55°C, V_CC = 3 V	5.47
		T_A = –40°C, V_CC = 3 V	5.49
		T_A = 25°C, V_CC = 3 V	5.54
		T_A = 125°C, V_CC = 3 V	5.68
		T_A = 150°C, V_CC = 3 V	5.77
Active-mode current supply	ƒ_SMCLK = ƒ_DCO = 16 MHz	T_A = –55°C, V_CC = 2.2 V	5.46	mA
		T_A = –40°C, V_CC = 2.2 V	5.58
		T_A = 25°C, V_CC = 2.2 V	5.89
		T_A = 125°C, V_CC = 2.2 V	6.03
		T_A = 150°C, V_CC = 2.2 V	6.20
		T_A = –55°C, V_CC = 3 V	7.14
		T_A = –40°C, V_CC = 3 V	7.14
		T_A = 25°C, V_CC = 3 V	7.21
		T_A = 125°C, V_CC = 3 V	7.429
		T_A = 150°C, V_CC = 3 V	7.54

4.8 Low-Power-Mode Supply Currents Into AV_CC Excluding External Current – Electrical Characteristics⁽¹⁾⁽²⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
I_{LPM0, 1MHz}	Low-power mode 0 (LPM0) current⁽³⁾	ƒ_MCLK = 0 MHz, ƒ_SMCLK = ƒ_DCO = 1 MHz, ƒ_ACLK = 32,768 Hz, BCSCTL1 = CALBC1_1 MHZ, DCOCTL = CALDCO_1 MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0	T_A = –55°C to 85°C, V_CC = 2.2 V	68	83	μA
			T_A = 105°C, V_CC = 2.2 V	83	98
			T_A = 150°C, V_CC = 2.2 V	210
			T_A = –55°C to 85°C, V_CC = 3 V	87	105
			T_A = 105°C, V_CC = 3 V	100	125
			T_A = 150°C, V_CC = 3 V	240
I_{LPM0, 100kHz}	Low-power mode 0 (LPM0) current⁽³⁾	ƒ_MCLK = 0 MHz, ƒ_SMCLK = ƒ_{DCO(0, 0)} ≉ 100 kHz, ƒ_ACLK = 0 Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 1	T_A = –55°C to 85°C, V_CC = 2.2 V	37	49	μA
			T_A = 105°C, V_CC = 2.2 V	50	62
			T_A = 150°C, V_CC = 2.2 V	160
			T_A = –55°C to 85°C, V_CC = 3 V	40	55
			T_A = 105°C, V_CC = 3 V	57	73
			T_A = 150°C, V_CC = 3 V	185
I_LPM2	Low-power mode 2 (LPM2) current⁽⁴⁾	ƒ_MCLK = ƒ_SMCLK= 0 MHz, ƒ_DCO = 1 MHz, ƒ_ACLK = 32,768 Hz, BCSCTL1 = CALBC1_1 MHZ, DCOCTL = CALDCO_1 MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0	T_A = –55°C to 85°C, V_CC = 2.2 V	23	33	μA
			T_A = 105°C, V_CC = 2.2 V	35	46
			T_A = 150°C, V_CC = 2.2 V	148
			T_A = –55°C to 85°C, V_CC = 3 V	25	36
			T_A = 105°C, V_CC = 3 V	40	55
			T_A = 150°C, V_CC = 3 V	168
I_LPM3,LFXT1	Low-power mode 3 (LPM3) current⁽⁴⁾	ƒ_DCO = ƒ_MCLK = ƒ_SMCLK = 0 MHz, ƒ_ACLK = 32,768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0	T_A = –55°C, V_CC = 2.2 V	0.8	1.2	μA
			T_A = 25°C, V_CC = 2.2 V	1	1.3
			T_A = 85°C, V_CC = 2.2 V	4.6	7
			T_A = 105°C, V_CC = 2.2 V	14	24
			T_A = –55°C, V_CC = 3 V	0.9	1.3
			T_A = 25°C, V_CC = 3 V	1.1	1.5
			T_A = 85°C, V_CC = 3 V	5.5	8
			T_A = 105°C, V_CC = 3 V	17	30
I_LPM3,VLO	Low-power mode 3 current, (LPM3)⁽⁴⁾	ƒ_DCO = ƒ_MCLK = ƒ_SMCLK = 0 MHz, ƒ_ACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0	T_A = –55°C, V_CC = 2.2 V	0.4	1	μA
			T_A = 25°C, V_CC = 2.2 V	0.5	1
			T_A = 85°C, V_CC = 2.2 V	4.3	6.5
			T_A = 105°C, V_CC = 2.2 V	14	24
			1T_A = 50°C, V_CC = 2.2 V	125
			T_A = –55°C, V_CC = 3 V	0.6	1.2
			T_A = 25°C, V_CC = 3 V	0.6	1.2
			T_A = 85°C, V_CC = 3 V	5	7.5
			T_A = 105°C, V_CC = 3 V	16.5	29.5
			T_A = 150°C, V_CC = 3 V	130
I_LPM4	Low-power mode 4 (LPM4) current⁽⁵⁾	ƒ_DCO = ƒ_MCLK = ƒ_SMCLK = 0 MHz, ƒ_ACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1	T_A = –55°C, V_CC = 2.2 V	0.1	0.5	μA
			T_A = 25°C, V_CC = 2.2 V	0.1	0.5
			T_A = 85°C, V_CC = 2.2 V	4	6
			T_A = 105°C, V_CC = 2.2 V	13	23
			T_A = 150°C, V_CC = 2.2 V	125
			T_A = –55°C, V_CC = 3 V	0.2	0.5
			T_A = 25°C, V_CC = 3 V	0.2	0.5
			T_A = 85°C, V_CC = 3 V	4.7	7
			T_A = 105°C, V_CC = 3 V	14	24
			T_A = 150°C, V_CC = 3 V	146

(1) All inputs are tied to 0 V or V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9 pF.

(3) Current for brownout and WDT clocked by SMCLK included.

(4) Current for brownout and WDT clocked by ACLK included.

(5) Current for brownout included.

4.9 Typical Characteristics – LPM4 Current

Figure 4-5 I_LPM4 -- LPM4 Current vs Temperature

4.10 Schmitt-Trigger Inputs (Ports P1 Through P6, and RST/NMI, JTAG, XIN, and XT2IN)⁽¹⁾ – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IT+	Positive-going input threshold voltage		0.45 x V_CC		0.75 x V_CC	V
		V_CC = 2.2 V	1.00		1.65
		V_CC = 3 V	1.35		2.25
V_IT–	Negative-going input threshold voltage		0.25 x V_CC		0.55 x V_CC	V
		V_CC = 2.2 V	0.55		1.20
		V_CC = 3 V	0.75		1.65
V_hys	Input voltage hysteresis (V_IT+ – V_IT–)	V_CC = 2.2 V	0.2		1	V
V_hys	Input voltage hysteresis (V_IT+ – V_IT–)	V_CC = 3 V	0.3		1	V
R_Pull	Pullup/pulldown resistor	For pullup: V_IN = V_SS For pulldown: V_IN = V_CC	20	35	50	kΩ
C_I	Input capacitance	V_IN = V_SS or V_CC		5		pF

(1) XIN and XT2IN in bypass mode only.

4.11 Inputs (Ports P1 and P2) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
t_(int)	External interrupt timing	Port P1, P2: P1.x to P2.x, External trigger pulse width to set interrupt flag⁽¹⁾, V_CC = 2.2 V or 3 V	20		ns

(1) An external signal sets the interrupt flag every time the minimum interrupt pulse width t_(int) is met. It may be set even with trigger signals shorter than t_(int).

4.12 Leakage Current (Ports P1 Through P6) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_lkg(Px.x)	High-impedance leakage current	See ⁽¹⁾ and ⁽²⁾, V_CC = 2.2 V or 3 V		±250		nA

(1) The leakage current is measured with V_SS or V_CC applied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.

4.13 Standard Inputs - RST/NMI – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_IL	Low-level input voltage	V_CC = 2.2 V or 3 V	V_SS	V_SS + 0.6	V
V_IH	High-level input voltage	V_CC = 2.2 V or 3 V	0.8 x V_CC	V_CC	V

4.14 Outputs (Ports P1 Through P6) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_OH	High-level output voltage	I_OH(max)= –1.5 mA⁽¹⁾, V_CC = 2.2 V	V_CC– 0.25	V_CC	V
		I_OH(max)= –6 mA⁽²⁾, V_CC = 2.2 V	V_CC – 0.6	V_CC
		I_OH(max)= –1.5 mA⁽¹⁾, V_CC = 3 V	V_CC – 0.25	V_CC
		I_OH(max) = –6 mA⁽²⁾, V_CC = 3 V	V_CC – 0.6	V_CC
V_OL	Low-level output voltage	I_OL(max) = 1.5 mA⁽¹⁾, V_CC = 2.2 V	V_SS	V_SS+0.25	V
		I_OL(max) = 6 mA⁽²⁾, V_CC = 2.2 V	V_SS	V_SS+0.6
		I_OL(max) = 1.5 mA⁽¹⁾, V_CC = 3 V	V_SS	V_SS+0.25
		I_OL(max) = 6 mA⁽²⁾, V_CC = 3 V	V_SS	V_SS+0.6

(1) The maximum total current, I_OH(max) and I_OL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop specified.

(2) The maximum total current, I_OH(max) and I_OL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.

4.15 Output Frequency (Ports P1 Through P6) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ƒ_Px.y	Port output frequency (with load)	P1.4/SMCLK, C_L = 20 pF, R_L = 1 kΩ⁽¹⁾⁽²⁾	V_CC = 2.2 V	DC		10	MHz
ƒ_Px.y	Port output frequency (with load)	P1.4/SMCLK, C_L = 20 pF, R_L = 1 kΩ⁽¹⁾⁽²⁾	V_CC = 3 V	DC		12	MHz
ƒ_{Port_CLK}	Clock output frequency	P2.0/ACLK/CA2, P1.4/SMCLK, C_L = 20 pF⁽²⁾	V_CC = 2.2 V	DC		12	MHz
ƒ_{Port_CLK}	Clock output frequency	P2.0/ACLK/CA2, P1.4/SMCLK, C_L = 20 pF⁽²⁾	V_CC = 3 V	DC		16	MHz
t_(Xdc)	Duty cycle of output frequency	P5.6/ACLK, C_L = 20 pF, LF mode		30%	50%	70%
		P5.6/ACLK, C_L = 20 pF, XT1 mode		40%	50%	60%
		P5.4/MCLK, C_L = 20 pF, XT1 mode		40%		60%
		P5.4/MCLK, C_L = 20 pF, DCO		50% – 15 ns	50%	50% + 15 ns
		P1.4/SMCLK, C_L = 20 pF, XT2 mode		40%		60%
		P1.4/SMCLK, C_L = 20 pF, DCO		50% – 15 ns		50% + 15 ns

(1) A resistive divider with 2 times 0.5 kΩ between V_CC and V_SS is used as load. The output is connected to the center tap of the divider.

(2) The output voltage reaches at least 10% and 90% V_CC at the specified toggle frequency.

4.16 Typical Characteristics – Outputs

Figure 4-6

Figure 4-8

Figure 4-7

Figure 4-9

4.17 POR/Brownout Reset (BOR) – Electrical Characteristics⁽¹⁾⁽²⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_CC(start)	See Figure 4-10	dV_CC/dt ≤ 3 V/s		0.7 × V_{(B_IT–)}		V
V_{(B_IT–)}	See Figure 4-10 through Figure 4-12	dV_CC/dt ≤ 3 V/s			1.71	V
V_{hys(B_IT–)}	See Figure 4-10	dV_CC/dt ≤ 3 V/s	70	130	210	mV
t_d(BOR)	See Figure 4-10				2000	μs
t_(reset)	Pulse length needed at RST/NMI pin to accepted reset internally	V_CC = 2.2 V or 3 V	2			μs

(1) The current consumption of the brownout module is already included in the I_CC current consumption data. The voltage level V_{(B_IT–)} + V_{hys(B_IT–} ₎ is ≤ 1.8 V.

(2) During power up, the CPU begins code execution following a period of t_d(BOR) after V_CC = V_{(B_IT–)} + V_{hys(B_IT–)}. The default DCO settings must not be changed until V_CC ≥ V_CC(min), where V_CC(min) is the minimum supply voltage for the desired operating frequency.

Figure 4-10 POR/Brownout Reset (BOR) vs Supply Voltage

4.18 Typical Characteristics - POR/Brownout Reset (BOR)

Figure 4-11 V_CC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal

Figure 4-12 V_CC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

4.19 SVS (Supply Voltage Supervisor/Monitor) - Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
t_(SVSR)	dV_CC/dt > 30 V/ms (see Figure 4-13)		5		150	μs
t_(SVSR)	dV_CC/dt ≤ 30 V/ms				2000	μs
t_d(SVSon)	SVSON, switch from VLD = 0 to VLD ≠ 0, V_CC = 3 V		20	150		μs
t_settle	VLD ≠ 0 (see ⁽¹⁾)				12	μs
V_(SVSstart)	VLD ≠ 0, V_CC/dt ≤ 3 V/s (see Figure 4-13)			1.55	1.7	V
V_{hys(SVS_IT-)}	V_CC/dt ≤ 3 V/s (see Figure 4-13)	VLD = 1	70	120	210	mV
	V_CC/dt ≤ 3 V/s (see Figure 4-13)	VLD = 2 to 14	V_{(SVS_IT-)} × 0.004		V_{(SVS_IT-)} × 0.016	V
	V_CC/dt ≤ 3 V/s (see Figure 4-13), External voltage applied on A7	VLD = 15	4.4		20	mV
V_{(SVS_IT-)}	V_CC/dt ≤ 3 V/s (see Figure 4-13 and Figure 4-14)	VLD = 1	1.8	1.9	2.05	V
		VLD = 2	1.94	2.1	2.25
		VLD = 3	2.05	2.2	2.37
		VLD = 4	2.14	2.3	2.48
		VLD = 5	2.24	2.4	2.6
		VLD = 6	2.33	2.5	2.71
		VLD = 7	2.46	2.65	2.86
		VLD = 8	2.58	2.8	3
		VLD = 9	2.69	2.9	3.13
		VLD = 10	2.83	3.05	3.29
		VLD = 11	2.94	3.2	3.42
		VLD = 12	3.11	3.35	3.61⁽²⁾
		VLD = 13	3.24	3.5	3.76⁽²⁾
		VLD = 14	3.43	3.7⁽²⁾	3.99⁽²⁾
	V_CC/dt ≤ 3 V/s (see Figure 4-13 and Figure 4-14), External voltage applied on A7	VLD = 15	1.1	1.2	1.3
I_CC(SVS)⁽³⁾	VLD ≠ 0, V_CC = 2.2 V/3 V			10	15	μA

(1) t_settle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value between 2 and 15. The overdrive is assumed to be > 50 mV.

(2) The recommended operating voltage range is limited to 3.6 V.

(3) The current consumption of the SVS module is not included in the I_CC current consumption data.

4.20 Typical Characteristics - SVS

Figure 4-13 SVS Reset (SVSR) vs Supply Voltage

Figure 4-14 V_CC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)

4.21 Main DCO Characteristics

All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter S_DCO.
Modulation control bits MODx select how often ƒ_{DCO(RSEL,DCO+1)} is used within the period of 32 DCOCLK cycles. The frequency ƒ_{DCO(RSEL,DCO)} is used for the remaining cycles. The frequency is an average equal to:

Equation 1. MSP430F2619S-HT equation1_las530.gif

4.22 DCO Frequency – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_CC	Supply voltage range	RSELx < 14	1.8		3.6	V
		RSELx = 14	2.2		3.6
		RSELx = 15	3.0		3.6
ƒ_DCO(0,0)	DCO frequency (0, 0)	RSELx = 0, DCOx = 0, MODx = 0, V_CC = 2.2 V or 3 V	0.06		0.14	MHz
ƒ_DCO(0,3)	DCO frequency (0, 3)	RSELx = 0, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	0.07		0.17	MHz
ƒ_DCO(1,3)	DCO frequency (1, 3)	RSELx = 1, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	0.10		0.20	MHz
ƒ_DCO(2,3)	DCO frequency (2, 3)	RSELx = 2, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	0.14		0.28	MHz
ƒ_DCO(3,3)	DCO frequency (3, 3)	RSELx = 3, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	0.20		0.40	MHz
ƒ_DCO(4,3)	DCO frequency (4, 3)	RSELx = 4, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	0.28		0.54	MHz
ƒ_DCO(5,3)	DCO frequency (5, 3)	RSELx = 5, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	0.39		0.77	MHz
ƒ_DCO(6,3)	DCO frequency (6, 3)	RSELx = 6, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	0.54		1.06	MHz
ƒ_DCO(7,3)	DCO frequency (7, 3)	RSELx = 7, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	0.80		1.50	MHz
ƒ_DCO(8,3)	DCO frequency (8, 3)	RSELx = 8, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	1.10		2.10	MHz
ƒ_DCO(9,3)	DCO frequency (9, 3)	RSELx = 9, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	1.60		3.00	MHz
ƒ_DCO(10,3)	DCO frequency (10, 3)	RSELx = 10, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	2.50		4.30	MHz
ƒ_DCO(11,3)	DCO frequency (11, 3)	RSELx = 11, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	3.00		5.50	MHz
ƒ_DCO(12,3)	DCO frequency (12, 3)	RSELx = 12, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	4.30		7.30	M Hz
ƒ_DCO(13,3)	DCO frequency (13, 3)	RSELx = 13, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	6.00		9.60	MHz
ƒ_DCO(14,3)	DCO frequency (14, 3)	RSELx = 14, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	8.60		13.9	MHz
ƒ_DCO(15,3)	DCO frequency (15, 3)	RSELx = 15, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V	12.0		18.5	MHz
ƒ_DCO(15,7)	DCO frequency (15, 7)	RSELx = 15, DCOx = 7, MODx = 0, V_CC = 2.2 V or 3 V	16.0		26.0	MHz
S_RSEL	Frequency step between range RSEL and RSEL+1	S_RSEL = ƒ_{DCO(RSEL+1,DCO)}/ƒ_{DCO(RSEL,DCO)}, V_CC = 2.2 V or 3 V			1.55	ratio
S_DCO	Frequency step between tap DCO and DCO+1	S_DCO = ƒ_{DCO(RSEL,DCO+1)}/ƒ_{DCO(RSEL,DCO)}, V_CC = 2.2 V or 3 V	1.05	1.08	1.12	ratio
Duty cycle		Measured at P1.4/SMCLK, V_CC = 2.2 V or 3 V	40%	50%	60%

4.23 Calibrated DCO Frequencies (Tolerance at Calibration) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Frequency tolerance at calibration		T_A = 25°C, V_CC = 3 V	–1%	±0.2%	1%
ƒ_{CAL(1 MHz)}	1-MHz calibration value	BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms T_A = 25°C, V_CC = 3 V	0.990	1	1.010	MHz
ƒ_{CAL(8 MHz)}	8-MHz calibration value	BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms T_A = 25°C, V_CC = 3 V	7.920	8	8.080	MHz
ƒ_{CAL(12 MHz)}	12-MHz calibration value	BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms T_A = 25°C, V_CC = 3 V	11.88	12	12.12	MHz
ƒ_{CAL(16 MHz)}	16-MHz calibration value	BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms T_A = 25°C, V_CC = 3 V	15.84	16	16.16	MHz

4.24 Calibrated DCO Frequencies (Tolerance Over Temperature) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
1-MHz tolerance over temperature		T_A = 0°C to 85°C, V_CC = 3 V		–2.5%	±0.5%	2.5%
8-MHz tolerance over temperature		T_A = 0°C to 85°C, V_CC = 3 V		–2.5%	±1.0%	2.5%
12-MHz tolerance over temperature		T_A = 0°C to 85°C, V_CC = 3 V		–2.5%	±1.0%	2.5%
16-MHz tolerance over temperature		T_A = 0°C to 85°C, V_CC = 3 V		–3.0%	±2.0%	3.0%
ƒ_CAL(1MHz)	1-MHz calibration value	BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms T_A = 0°C to 85°C	V_CC = 2.2 V	0.970	1	1.030	MHz
			V_CC = 3 V	0.975	1	1.025
			V_CC = 3.6 V	0.970	1	1.030
ƒ_CAL(8MHz)	8-MHz calibration value	BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms T_A = 0°C to 85°C	V_CC = 2.2 V	7.760	8	8.400	MHz
			V_CC = 3 V	7.800	8	8.200
			V_CC = 3.6 V	7.600	8	8.240
ƒ_CAL(12MHz)	12-MHz calibration value	BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms T_A = 0°C to 85°C	V_CC = 2.2 V	11.70	12	12.30	MHz
			V_CC = 3 V	11.70	12	12.30
			V_CC = 3.6 V	11.70	12	12.30
ƒ_CAL(16MHz)	16-MHz calibration value	BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms T_A = 0°C to 85°C	V_CC = 3 V	15.52	16	16.48	MHz
ƒ_CAL(16MHz)	16-MHz calibration value		V_CC = 3.6 V	15.00	16	16.48	MHz

4.25 Calibrated DCO Frequencies (Tolerance Over Supply Voltage V_CC) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
1-MHz tolerance over V_CC		T_A = 25°C, V_CC = 1.8 V to 3.6 V	–3%	±2%	3%
8-MHz tolerance overV_CC		T_A = 25°C, V_CC = 1.8 V to 3.6 V	–3%	±2%	3%
12-MHz tolerance over V_CC		T_A = 25°C, V_CC = 2.2 V to 3.6 V	–3%	±2%	3%
16-MHz tolerance over V_CC		T_A = 25°C, V_CC = 3 V to 3.6 V	–6%	±2%	3%
ƒ_CAL(1MHz)	1-MHz calibration value	BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms, T_A = 25°C, V_CC = 1.8 V to 3.6 V	0.970	1	1.030	MHz
ƒ_CAL(8MHz)	8-MHz calibration value	BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms, T_A = 25°C, V_CC = 1.8 V to 3.6 V	7.760	8	8.240	MHz
ƒ_CAL(12MHz)	12-MHz calibration value	BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms, T_A = 25°C, V_CC = 2.2 V to 3.6 V	11.64	12	12.36	MHz
ƒ_CAL(16MHz)	16-MHz calibration value	BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms, T_A = 25°C, V_CC = 3 V to 3.6 V	15.00	16	16.48	MHz

4.26 Calibrated DCO Frequencies (Overall Tolerance) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
1-MHz tolerance over temperature		T_A = –55°C to 150°C, V_CC = 1.8 V to 3.6 V	–5%	±2%	5%
8-MHz tolerance over temperature		T_A = –55°C to 150°C, V_CC = 1.8 V to 3.6 V	–5%	±2%	5%
12-MHz tolerance over temperature		T_A = –55°C to 150°C, V_CC = 2.2 V to 3.6 V	–5%	±2%	5%
16-MHz tolerance over temperature		T_A = –55°C to 150°C, V_CC = 3 V to 3.6 V	–6%	±3%	6%
ƒ_CAL(1MHz)	1-MHz calibration value	BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms, T_A = –55°C to 150°C, V_CC = 1.8 V to 3.6 V	.950	1	1.050	MHz
ƒ_CAL(8MHz)	8-MHz calibration value	BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms, T_A = –55°C to 150°C, V_CC = 1.8 V to 3.6 V	7.6	8	8.4	MHz
ƒ_CAL(12MHz)	12-MHz calibration value	BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms, T_A = –55°C to 150°C, V_CC = 2.2 V to 3.6 V	11.4	12	12.6	MHz
ƒ_CAL(16MHz)	16-MHz calibration value	BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms, T_A = –55°C to 150°C, V_CC = 3 V to 3.6 V	15.00	16	17.00	MHz

4.27 Typical Characteristics – Calibrated DCO Frequency

Figure 4-15 Calibrated 1-MHz DCO Frequency vs V_CC

Figure 4-17 Calibrated 12-MHz DCO Frequency vs V_CC

Figure 4-16 Calibrated 8-MHz DCO Frequency vs V_CC

Figure 4-18 Calibrated 16-MHz DCO Frequency vs V_CC

4.28 Wake-Up From Low-Power Modes (LPM3/4) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_DCO,LPM3/4	DCO clock wake-up time from LPM3/4⁽¹⁾	BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, V_CC = 2.2 V or 3 V		2	μs
		BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, V_CC = 2.2 V or 3 V		1.5
		BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, V_CC = 3 V		1
		BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, V_CC = 3 V		1
t_CPU,LPM3/4	CPU wake-up time from LPM3/4⁽²⁾		1/ƒ_MCLK+ t_Clock,LPM3/4

(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK).

(2) Parameter applicable only if DCOCLK is used for MCLK.

4.29 Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4

Figure 4-19 Clock Wake-Up Time From LPM3 vs DCO Frequency

4.30 DCO With External Resistor R_OSC – Electrical Characteristics⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		TYP	UNIT
ƒ_DCO,ROSC	DCO output frequency with R_OSC	DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, T_A = 25°C	V_CC = 2.2 V	1.8	MHz
ƒ_DCO,ROSC	DCO output frequency with R_OSC	DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, T_A = 25°C	V_CC = 3 V	1.95	MHz
D_t	Temperature drift	DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V		±0.1	%/°C
D_V	Drift with V_CC	DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, V_CC = 2.2 V or 3 V		10	%/V

(1) R_OSC = 100 kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and T_K = ±50 ppm/°C

4.31 Typical Characteristics - DCO With External Resistor R_OSC

Figure 4-20 DCO Frequency vs R_OSC,
V_CC = 2.2 V, T_A = 25°C

MSP430F2619S-HT dco_frq_v_temp_las697.gif

Figure 4-22 DCO Frequency vs Temperature,
V_CC = 3.0 V

Figure 4-21 DCO Frequency vs R_OSC,
V_CC = 3.0 V, T_A = 25°C

MSP430F2619S-HT dco_frq_vs_vcc_las697.gif

Figure 4-23 DCO Frequency vs V_CC,
T_A = 25°C

4.32 Crystal Oscillator (LFXT1) Low-Frequency Modes – Electrical Characteristics⁽¹⁾⁽²⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ƒ_LFXT1,LF	LFXT1 oscillator crystal frequency, LF mode 0, 1	XTS = 0, LFXT1Sx = 0 or 1, V_CC = 1.8 V to 3.6 V			32,768		Hz
ƒ_{LFXT1,LF,logic}	LFXT1 oscillator logic-level square-wave input frequency, LF mode	XTS = 0, LFXT1Sx = 3, V_CC = 1.8 V to 3.6 V		10,000	32,768	50,000	Hz
OA_LF	Oscillation allowance for LF crystals	XTS = 0, LFXT1Sx = 0; ƒ_LFXT1,LF = 32,768 kHz, C_L,eff = 6 pF			500		kΩ
OA_LF	Oscillation allowance for LF crystals	XTS = 0, LFXT1Sx = 0;ƒ_LFXT1,LF = 32,768 kHz, C_L,eff = 12 pF			200		kΩ
C_L,eff	Integrated effective load capacitance, LF mode⁽³⁾	XTS = 0	XCAPx = 0		1		pF
			XCAPx = 1		5.5
			XCAPx = 2		8.5
			XCAPx = 3		11
Duty cycle	LF mode	XTS = 0, Measured at P1.4/ACLK, ƒ_LFXT1,LF = 32,768 Hz, V_CC = 2.2 V or 3 V		30%	50%	70%
ƒ_Fault,LF	Oscillator fault frequency threshold, LF mode ⁽⁵⁾	XTS = 0, LFXT1Sx = 3⁽⁴⁾, V_CC = 2.2 V or 3 V		10		10,000	Hz

(1) To improve EMI on the LFXT1 oscillator the following guidelines should be observed:

Keep as short of a trace as possible between the device and the crystal.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.

(2) LFXT1 in 32-KHz mode is specified to function only between –55°C to 105°C. This module is know to fail above 110°C. For further info contact TI support.

(3) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal.

(4) Measured with logic-level input frequency, but also applies to operation with crystals.

(5) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag.

4.33 Internal Very-Low-Power, Low-Frequency Oscillator (VLO) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ƒ_VLO	VLO frequency	T_A = –55°C to 85°C, V_CC = 2.2 V or 3 V	4	12	20	kHz
ƒ_VLO	VLO frequency	T_A = 150°C, V_CC = 2.2 V or 3 V			22	kHz
dƒ_VLO/dT	VLO frequency temperature drift	See ⁽¹⁾, V_CC = 2.2 V or 3 V		0.5	0.8	%/°C
dƒ_VLO/dV_CC	VLO frequency supply voltage drift	See ⁽²⁾, T_A = 25°C, V_CC = 1.8 V to 3.6V		4		%/V

(1) Calculated using the box method:
S Version: (MAX(–55 to 150°C) – MIN(–55 to 150°C))/MIN(–55 to 150°C)/(150°C – (–55°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8V to 3.6 V))/MIN(1.8 V to 3.6 V)/(3.6 V – 1.8 V)

4.34 Crystal Oscillator (LFXT1) High Frequency Modes – Electrical Characteristics⁽⁵⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ƒ_LFXT1,HF0	LFXT1 oscillator crystal frequency, HF mode 0	XTS = 1, LFXT1Sx = 0, V_CC = 1.8 V to 3.6 V		0.4		1	MHz
ƒ_LFXT1,HF1	LFXT1 oscillator lcrystal frequency, HF mode 1	XTS = 1, LFXT1Sx = 1, V_CC = 1.8 V to 3.6 V		1		4	MHz
ƒ_LFXT1,HF2	LFXT1 oscillator crystal frequency, HF mode 2	XTS = 1, LFXT1Sx = 2	V_CC = 1.8 V to 3.6 V	2		10	MHz
			V_CC = 2.2 V to 3.6 V	2		12
			V_CC = 3 V to 3.6 V	2		16
ƒ_{LFXT1,HF,logic}	LFXT1 oscillator logic-level square-wave input frequency, HF mode	XTS = 1, LFXT1Sx = 3	V_CC = 1.8 V to 3.6 V	0.4		10	MHz
			V_CC = 2.2 V to 3.6 V	0.4		12
			V_CC = 3 V to 3.6 V	0.4		16
OA_HF	Oscillation allowance for HF crystals (see Figure 4-24 and Figure 4-25)	XTS = 0, LFXT1Sx = 0; ƒ_LFXT1,HF = 1 MHz, C_L,eff = 15 pF			2700		Ω
		XTS = 0, LFXT1Sx = 1 ƒ_LFXT1,HF = 4 MHz, C_L,eff = 15 pF			800
		XTS = 0, LFXT1Sx = 2 ƒ_LFXT1,HF = 16 MHz, C_L,eff = 15 pF			300
C_L,eff	Integrated effective load capacitance, HF mode⁽¹⁾	XTS = 1⁽²⁾			1		pF
Duty cycle	HF mode	XTS = 1, Measured at P1.4/ACLK, ƒ_LFXT1,HF = 10 MHz, V_CC = 3 V		40%	50%	60%
Duty cycle	HF mode	XTS = 1, Measured at P1.4/ACLK, ƒ_LFXT1,HF = 16 MHz, V_CC = 3 V		40%	50%	60%
ƒ_Fault,HF	Oscillator fault frequency, HF mode⁽⁴⁾	XTS = 1, LFXT1Sx = 3⁽³⁾, V_CC = 2.2 V or 3 V		30		300	kHz

(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal.

(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(3) Measured with logic-level input frequency, but also applies to operation with crystals

(4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag.

(5) To improve EMI on the LFXT1 oscillator the following guidelines should be observed:

Keep as short of a trace as possible between the device and the crystal.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.

4.35 Typical Characteristics – LFXT1 Oscillator in HF Mode (XTS = 1)

Figure 4-24 Oscillation Allowance vs Crystal Frequency, C_L,eff = 15 pF, T_A = 25°C

Figure 4-25 XT Oscillator Supply Current vs Crystal Frequency, C_L,eff = 15 pF, T_A = 25°C

4.36 Crystal Oscillator (XT2) – Electrical Characteristics⁽⁵⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ƒ_XT2	XT2 oscillator crystal frequency, mode 0	XT2Sx = 0, V_CC = 1.8 V to 3.6 V		0.4		0.9	MHz
ƒ_XT2	XT2 oscillator lcrystal frequency, mode 1	XT2Sx = 1, V_CC = 1.8 V to 3.6 V		1		4	MHz
ƒ_XT2	XT2 oscillator crystal frequency, mode 2	XT2Sx = 2	V_CC = 1.8 V to 3.6 V	2		10	MHz
			V_CC = 2.2 V to 3.6 V	2		12
			V_CC = 3 V to 3.6 V	2		16
ƒ_XT2	XT2 oscillator logic-level square-wave input frequency,	XT2Sx = 3	V_CC = 1.8 V to 3.6 V	0.4		10	MHz
			V_CC = 2.2 V to 3.6 V	0.4		12
			V_CC = 3 V to 3.6 V	0.4		16
OA	Oscillation allowance (see Figure 4-26 and Figure 4-27)	XT2Sx = 0, ƒ_XT2 = 1 MHz; C_L,eff = 15 pF			2700		Ω
		XT2Sx = 1, ƒ_XT2 = 4MHz; C_L,eff = 15 pF			800
		XT2Sx = 2, ƒ_{XT1, HF} = 16 MHz; C_L,eff = 15 pF			300
C_L,eff	Integrated effective load capacitance, HF mode⁽¹⁾	See ⁽²⁾			1		pF
Duty cycle	HF mode	Measured at P1.4/SMCLK, ƒ_XT2 = 10 MHz, V_CC = 2.2 V or 3 V		40%	50%	60%
Duty cycle	HF mode	Measured at P1.4/SMCLK, ƒ_XT2 = 16 MHz, V_CC = 2.2 V or 3 V		40%	50%	60%
ƒ_Fault	Oscillator fault frequency, HF mode⁽⁴⁾	XT2Sx = 3⁽³⁾, V_CC = 2.2 V or 3 V		30		300	kHz

(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(3) Measured with logic-level input frequency, but also applies to operation with crystals.

(4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag.

(5) To improve EMI on the LFXT1 oscillator the following guidelines should be observed:

Keep as short of a trace as possible between the device and the crystal.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.

4.37 Typical Characteristics – XT2 Oscillator

MSP430F2619S-HT osc_all_vs_crystal2_las697.gif

Figure 4-26 Oscillation Allowance vs Crystal Frequency, C_L,eff = 15 pF, T_A = 25°C

Figure 4-27 XT2 Oscillator Supply Current vs Crystal Frequency, C_L,eff = 15 pF, T_A = 25°C

4.38 Timer_A – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	MAX	UNIT
ƒ_TA	Timer_A clock frequency	Internal: SMCLK, ACLK, External: TACLK, INCLK, Duty cycle = 50% ±10%	V_CC = 2.2 V		10	MHz
ƒ_TA	Timer_A clock frequency		V_CC = 3 V		16	MHz
t_TA,cap	Timer_A, capture timing	TA0, TA1, TA2, V_CC = 2.2 V or 3 V		20		ns

4.39 Timer_B – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	MAX	UNIT
ƒ_TB	Timer_B clock frequency	Internal: SMCLK, ACLK, External: TBCLK, Duty cycle = 50% ±10%	V_CC = 2.2 V		10	MHz
ƒ_TB	Timer_B clock frequency		V_CC = 3 V		16	MHz
t_TB,cap	Timer_B, capture timing	TB0, TB1, TB2, V_CC = 2.2 V or 3 V		20		ns

4.40 USCI (UART Mode) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ƒ_USCI	USCI input clock frequency	Internal: SMCLK, ACLK, External: UCLK; Duty cycle = 50% ±10%			ƒ_SYSTEM	MHz
ƒ_BITCLK	BITCLK clock frequency (equals baud rate in MBaud)	V_CC = 2.2 V or 3 V			1	MHz
t_τ	UART receive deglitch time⁽¹⁾	V_CC = 2.2 V	50	150	600	ns
t_τ	UART receive deglitch time⁽¹⁾	V_CC = 3 V	50	150	600	ns

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their width should exceed the maximum specification of the deglitch time.

4.41 USCI (SPI Master Mode) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾ (see Figure 4-28 and Figure 4-29)

PARAMETER		TEST CONDITIONS		MIN	MAX	UNIT
ƒ_USCI	USCI input clock frequency	SMCLK, ACLK, Duty cycle = 50% ±10%			ƒ_SYSTEM	MHz
t_SU,MI	SOMI input data setup time	V_CC= 2.2 V		110		ns
t_SU,MI	SOMI input data setup time	V_CC = 3 V		75		ns
t_HD,MI	SOMI input data hold time	V_CC = 2.2 V		0		ns
t_HD,MI	SOMI input data hold time	V_CC = 3 V		0		ns
t_VALID,MO	SIMO output data valid time	UCLK edge to SIMO valid, C_L = 20 pF	V_CC = 2.2 V		30	ns
t_VALID,MO	SIMO output data valid time	UCLK edge to SIMO valid, C_L = 20 pF	V_CC = 3 V		20	ns

(1) ƒ_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(USCI)} + t_SU,SI(Slave), t_SU,MI(USCI) + t_{VALID,SO(Slave)}).
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

4.42 USCI (SPI Slave Mode) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾ (see Figure 4-30 and Figure 4-31)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
t_STE,LEAD	STE lead time, STE low to clock	V_CC = 2.2 V or 3 V			50		ns
t_STE,LAG	STE lag time, Last clock to STE high	V_CC = 2.2 V or 3 V		10			ns
t_STE,ACC	STE access time, STE low to SOMI data out	V_CC = 2.2 V or 3 V			50		ns
t_STE,DIS	STE disable time, STE high to SOMI high impedance	V_CC = 2.2 V or 3 V			50		ns
t_SU,SI	SIMO input data setup time	V_CC = 2.2 V		20			ns
t_SU,SI	SIMO input data setup time	V_CC = 3 V		15			ns
t_HD,SI	SIMO input data hold time	V_CC = 2.2 V		10			ns
t_HD,SI	SIMO input data hold time	V_CC = 3 V		10			ns
t_VALID,SO	SOMI output data valid time	UCLK edge to SOMI valid, C_L = 20 pF	V_CC = 2.2 V		75	110	ns
t_VALID,SO	SOMI output data valid time	UCLK edge to SOMI valid, C_L = 20 pF	V_CC = 3 V		50	75	ns

Figure 4-28 SPI Master Mode, CKPH = 0

Figure 4-29 SPI Master Mode, CKPH = 1

Figure 4-30 SPI Slave Mode, CKPH = 0

Figure 4-31 SPI Slave Mode, CKPH = 1

4.43 USCI (I2C Mode) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4-32)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ƒ_USCI	USCI input clock frequency	Internal: SMCLK, ACLK, External: UCLK, Duty cycle = 50% ± 10%		ƒ_SYSTEM		MHz
ƒ_SCL	SCL clock frequency	V_CC = 2.2 V or 3 V	0		400	kHz
t_HD,STA	Hold time (repeated) START	ƒ_SCL ≤ 100 kHz, V_CC = 2.2 V or 3 V	4.0			μs
t_HD,STA	Hold time (repeated) START	ƒ_SCL > 100 kHz, V_CC = 2.2 V or 3 V	0.6			μs
t_SU,STA	Set-up time for a repeated START	ƒ_SCL ≤ 100 kHz, V_CC = 2.2 V or 3 V	4.7			μs
t_SU,STA	Set-up time for a repeated START	ƒ_SCL > 100 kHz, V_CC = 2.2 V or 3 V	0.6			μs
t_HD,DAT	Data hold time	V_CC = 2.2 V or 3 V	0			ns
t_SU,DAT	Data set-up time	V_CC = 2.2 V or 3 V	250			ns
t_SU,STO	Set-up time for STOP	V_CC = 2.2 V or 3 V	4.0			μs
t_SP	Pulse width of spikes suppressed by input filter	V_CC = 2.2 V	50	150	600	ns
t_SP	Pulse width of spikes suppressed by input filter	V_CC = 3 V	50	100	600	ns

Figure 4-32 I2C Mode Timing

4.44 Comparator_A+ – Electrical Characteristics⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
I_(DD)		CAON = 1 CARSEL = 0 CAREF = 0	V_CC = 2.2 V		25	80	μA
I_(DD)		CAON = 1 CARSEL = 0 CAREF = 0	V_CC = 3 V		45	96	μA
I_{(Refladder/Refdiode)}		CAON = 1, CARSEL = 0, CAREF = 1/2/3 no load at P2 3/CA0/TA1 and P2.4/CA1/TA2	V_CC = 2.2 V or 3 V		30	50	μA
I_{(Refladder/Refdiode)}			V_CC = 3 V		45	71	μA
V_(IC)	Common-mode input voltage	CAON =1, V_CC = 2.2 V or 3 V		0		V_CC - 1	V
V_(Ref025)	Voltage at 0.25 V_CC node/V_CC	PCA0 = 1, CARSEL = 1, CAREF = 1, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2, V_CC = 2.2 V or 3 V		0.23	0.24	0.25	V
V_(Ref050)	Voltage at 0.5 V_CC node/V_CC	PCA0 = 1, CARSEL = 1, CAREF = 2, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2, V_CC = 2.2 V or 3 V		0.47	0.48	0.5	V
V_(RefVT)	See Figure 4-36 and Figure 4-37	PCA0 = 1, CARSEL = 1, CAREF = 3, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2, T_A = 85°C	V_CC = 2.2 V	390	480	540	mV
V_(RefVT)	See Figure 4-36 and Figure 4-37		V_CC = 3 V	400	490	550	mV
V_(offset)	Offset voltage	See ⁽²⁾, V_CC = 2.2 V or 3 V		–30		30	mV
V_hys	Input hysteresis	CAON=1, V_CC = 2.2 V or 3 V		0	0.7	1.4	mV
t_(response)	Response time, low-to-high and high-to-low⁽³⁾	T_A = 25°C, Overdrive 10 mV, Without filter: CAF = 0	V_CC = 2.2 V	80	165	300	ns
		T_A = 25°C, Overdrive 10 mV, Without filter: CAF = 0	V_CC = 3 V	70	120	240	ns
		T_A = 25°C, Overdrive 10 mV, Without filter: CAF = 1	V_CC = 2.2 V	1.4	1.9	2.8	µs
		T_A = 25°C, Overdrive 10 mV, Without filter: CAF = 1	V_CC = 3 V	0.9	1.5	2.2	µs

(1) The leakage current for the Comparator_A+ terminals is identical to I_lkg(Px.x) specification.

(2) The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.

(3) The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step, with Comparator_A+ already enabled (CAON = 1). If CAON is set at the same time, a settling time of up to 300 ns is added to the response time.

Figure 4-33 Block Diagram of Comparator_A Module

Figure 4-34 Overdrive Definition

Figure 4-35 Comparator_A+ Short Resistance Test Condition

4.45 Typical Characteristics – Comparator A+

Figure 4-36 V_(RefVT) vs Temperature, V_CC = 3 V

MSP430F2619S-HT Short_res_vs_vin_las697.gif

Figure 4-38 Short Resistance vs V_IN/V_CC

Figure 4-37 V_(RefVT) vs Temperature, V_CC = 2.2 V

4.46 12-Bit ADC Power-Supply and Input Range Conditions – Electrical Characteristics⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
AV_CC	Analog supply voltage range	AV_CC and DV_CC are connected together, AV_SS and DV_SS are connected together, V_(AVSS) = V_(DVSS) = 0 V		2.2		3.6	V
V_(P6.x/Ax)	Analog input voltage range ⁽²⁾	All P6.0/A0 to P6.7/A7 terminals. Analog inputs selected in ADC12MCTLx register and P6Sel.x = 1, 0 ≤ x ≤ 7, V_(AVSS) ≤ VP6.x/Ax ≤ V_(AVCC)		0		V_AVCC	V
I_ADC12	Operating supply current into AV_CC terminal⁽³⁾	ƒ_ADC10CLK = 5 MHz, ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0	V_CC = 2.2 V		0.65	0.8	mA
I_ADC12	Operating supply current into AV_CC terminal⁽³⁾		V_CC = 3 V		0.8	1	mA
I_REF+	Reference supply current, into AV_CC terminal⁽⁴⁾	ƒ_ADC12CLK = 5 MHz, ADC12ON = 0, REFON = 1, REF2_5V = 1, V_CC = 3 V			0.5	0.7	mA
		ƒ_ADC12CLK = 5 MHz, ADC12ON = 0, REFON = 1, REF2_5V = 0	V_CC = 2.2 V		0.5	0.7
		ƒ_ADC12CLK = 5 MHz, ADC12ON = 0, REFON = 1, REF2_5V = 0	V_CC = 3 V		0.5	0.7
C_I⁽⁵⁾	Input capacitance	Only one terminal selected at a time, P6.x/Ax, V_CC = 2.2 V				40	pF
R_I⁽⁵⁾	Input MUX ON resistance	0 V ≤ V_Ax ≤ V_AVCC, V_CC = 3 V				2000	Ω

(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.

(2) The analog input voltage range must be within the selected reference voltage range V_R+ to V_R– for valid conversion results.

(3) The internal reference supply current is not included in current consumption parameter I_ADC12.

(4) The internal reference current is supplied via terminal V_CC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

(5) Limits verified by design.

4.47 12-Bit ADC External Reference – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_eREF+	Positive external reference voltage input	V_eREF+ > V_REF-/VeREF-⁽¹⁾	1.4	V_AVCC	V
V_REF- /V_eREF+	Negative external reference voltage input	V_eREF+ > V_REF-/VeREF- ⁽²⁾	0	1.2	V
(V_eREF+ - V_REF- / V_eREF-)	Differential external reference voltage input	V_eREF+ > V_REF-/VeREF- ⁽³⁾	1.4	V_AVCC	V
I_VeREF+	Static input current	0 V ≤ V_eREF+ ≤ V_AVCC, V_CC = 2.2 V or 3 V		±1	µA
I_VREF-/VeREF-	Static input current	0 V ≤ V_eREF- ≤ V_AVCC, V_CC = 2.2 V or 3 V		±1	µA

(1) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements.

(2) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be appliedwith reduced accuracy requirements.

(3) The accuracy limitsminimum external differential reference voltage. Lower differential reference voltage levels may be appliedwith reduced accuracy requirements.

4.48 12-Bit ADC Built-In Reference – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_REF+	Positive built-in reference voltage output	REF2_5V = 1 (2.5 V) I_VREF+max ≤ I_VREF+ ≤ I_VREF+min	T_A = -55°C to 85°C, V_CC = 3 V	2.4	2.5	2.6	V
		REF2_5V = 1 (2.5 V) I_VREF+max ≤ I_VREF+ ≤ I_VREF+min	T_A = 150°C, V_CC = 3 V	2.37	2.5	2.64
		REF2_5V = 1 (1.5 V) I_VREF+max ≤ I_VREF+ ≤ I_VREF+min	T_A = -55°C to 85°C, V_CC = 2.2 V or 3 V	1.44	1.5	1.56
		REF2_5V = 1 (1.5 V) I_VREF+max ≤ I_VREF+ ≤ I_VREF+min	T_A = 150°C, V_CC = 2.2 V or 3 V	1.42	1.5	1.57
AV_CC(min)	AV_CC minimum voltage, positive built-in reference active	REF2_5V = 0, I_VREF+max ≤ I_VREF+ ≤ I_VREF+min		2.2			V
		REF2_5V = 1, –0.5 mA ≤ I_VREF+ ≤ I_VREF+min		2.8
		REF2_5V = 1, –1 mA ≤ I_VREF+ ≤ I_VREF+min		2.9
I_VREF+	Load current out of V_REF+ terminal	V_CC = 3 V		0.01		–0.5	mA
I_VREF+	Load current out of V_REF+ terminal	V_CC = 3 V		0.01		–1	mA
I_L(VREF)+⁽¹⁾	Load current regulation, V_REF+ terminal	I_VREF+ = 500 μA ± 100 μA, Analog input voltage V_Ax ≉ 0.75 V, REF2_5V = 0	V_CC = 3 V			±2	LSB
			V_CC = 3 V			±2
		I_VREF+ = 500 μA ± 100 μA, Analog input voltage V_Ax ≉ 1.25 V, REF2_5V = 1, V_CC = 3 V				±2
I_DL(VREF)+⁽²⁾	Load current regulation, V_REF+ terminal	I_VREF+ = 100 μA → 900 μA, C_VREF+ = 5 μF, at ≉ 0.5 V_REF+, Error of conversion result ≤ 1 LSB, V_CC = 3 V				20	ns
C_VREF+	Capacitance at pin V_REF+⁽³⁾	REFON = 1, 0 mA ≤ I_VREF+ ≤ I_VREF+max, V_CC = 2.2 V or 3 V		5	10		µF
T_REF+⁽¹⁾	Temperature coefficient of built-in reference	I_VREF+ is a constant in the range of 0 mA ≤ I_VREF+ ≤ 1 mA, V_CC = 2.2 V or 3 V				±100	ppm/°C
t_REFON ⁽¹⁾	Settling time of internal reference voltage⁽⁴⁾ (see Figure 4-39)	I_VREF+ = 0.5 mA, C_VREF+ = 10 μF, V_REF+ = 1.5 V, V_AVCC = 2.2 V				17	ms

(1) Limits characterized.

(2) Limits verified by design.

(3) The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests use two capacitors between pins V_REF+ and AV_SS and V_REF-/V_eREF- and AV_SS: 10 μF tantalum and 100 nF ceramic.

(4) The condition is that the error in a conversion started after t_REFON or t_RefBuf is less than ±0.5 LSB.

4.49 Typical Characteristics – ADC12

Figure 4-39 Typical Settling Time of Internal Reference t_REFON vs External Capacitor on V_REF+

MSP430F2619S-HT vs_vref_design_las697.gif

Figure 4-40 Supply Voltage and Reference Voltage Design V_REF-/V_eREF- External Supply

MSP430F2619S-HT vs_vref_design2_las697.gif

Figure 4-41 Supply Voltage and Reference Voltage Design V_REF-/V_eREF- = AV_SS, Internally Connected

4.50 12-Bit ADC Timing Parameters – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ƒ_ADC12CLK	ADC12 input clock frequency	For specified performance of ADC12 linearity parameters, V_CC = 2.2 V or 3 V		0.45	5	6.3	MHz
ƒ_ADC12OSC	ADC12 built-in oscillator frequency	ADC12DIV = 0, ƒ_ADC12CLK = ƒ_ADC12OSC , V_CC = 2.2 V or 3 V		3.7	5	6.3	MHz
t_CONVERT	Conversion time	ADC12 built-in oscillator, C_VREF+ ≥ 5 μF, ƒ_ADC12OSC = 3.7 MHz to 6.3 MHz, V_CC = 2.2 V or 3 V		2.06		3.51	μs
t_CONVERT	Conversion time	External ƒ_ADC12CLK from ACLK, MCLK, or SMCLK: ADC12SSEL ≠ 0		13 x ADC12DIV x 1/ƒ_ADC12CLK			μs
t_ADC12ON ⁽¹⁾	Turn-on settling time of the ADC	See⁽²⁾				100	ns
t_Sample⁽¹⁾	Sampling time	RS = 400 Ω, RI = 1000 Ω, CI = 30 pF, τ = [R_S + R_I] x C_I ⁽³⁾	V_CC = 3 V	1220			ns
t_Sample⁽¹⁾	Sampling time		V_CC = 2.2 V	1400			ns

(1) Limits verified by design.

(2) The condition is that the error in a conversion started after t_ADC12ON is less than ±0.5 LSB. The reference and input signal are already settled.

(3) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB: t_Sample = ln(2ⁿ⁺¹) x (R_S + R_I) x C_I+ 800 ns where n = ADC resolution = 12, R_S = external source resistance.

4.51 12-Bit ADC Linearity Parameters – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
E_I	Integral linearity error	1.4 V ≤ (V_eREF+ - V_REF-/V_eREF-) min ≤ 1.6 V, V_CC = 2.2 V or 3 V		±2	LSB
E_I	Integral linearity error	1.6 V < (V_eREF+ - V_REF-/V_eREF-) min ≤ V_AVCC, V_CC = 2.2 V or 3 V		±1.7	LSB
E_D	Differential linearity error	(V_eREF+ - V_REF-/V_eREF-)min ≤ (V_eREF+ - V_REF-/V_eREF-), C_VREF+ = 10 μF (tantalum) and 100 nF (ceramic), V_CC = 2.2 V or 3 V		±1	LSB
E_O	Offset error	(V_eREF+ - V_REF-/V_eREF-)min ≤ (V_eREF+ - V_REF-/V_eREF-), Internal impedance of source R_S < 100 Ω, C_VREF+ = 10 μF (tantalum) and 100 nF (ceramic), V_CC = 2.2 V or 3 V	±2	±4	LSB
E_G	Gain error	(V_eREF+ - V_REF-/V_eREF-)min ≤ (V_eREF+ - V_REF-/V_eREF-), C_VREF+ = 10 μF (tantalum) and 100 nF (ceramic), V_CC = 2.2 V or 3 V	±1.1	±2	LSB
E_T	Total unadjusted error	(V_eREF+ - V_REF-/V_eREF-)min ≤ (V_eREF+ - V_REF-/V_eREF-), C_VREF+ = 10 μF (tantalum) and 100 nF (ceramic), V_CC = 2.2 V or 3 V	±2	±5	LSB

4.52 12-Bit ADC Temperature Sensor and Built-In V_MID – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
I_SENSOR	Operating supply current into AV_CC terminal⁽²⁾	REFON = 0, INCH = 0Ah, ADC12ON = 1, T_A = 25°C, VCC = 2.2 V	V_CC = 2.2 V		40	120	μA
I_SENSOR	Operating supply current into AV_CC terminal⁽²⁾	REFON = 0, INCH = 0Ah, ADC12ON = 1, T_A = 25°C, VCC = 2.2 V	V_CC = 3 V		60	160	μA
V_Sensor⁽¹⁾	Sensor output voltage⁽³⁾	ADC12ON = 1, INCH = 0Ah, T_A = 0°C, V_CC = 2.2 V or 3 V			986		mV
TC_SENSOR⁽¹⁾		ADC12ON = 1, INCH = 0Ah, V_CC = 2.2 V or 3 V			3.55		mV/°C
t_{Sensor(sample)}⁽¹⁾	Sample time required if channel 10 is selected ⁽⁴⁾	ADC12ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB, V_CC = 2.2 V or 3 V		30			μs
I_VMID	Current into divider at channel 11⁽⁵⁾	ADC12ON = 1, INCH = 0Bh	V_CC = 2.2 V			NA	μA
I_VMID	Current into divider at channel 11⁽⁵⁾	ADC12ON = 1, INCH = 0Bh	V_CC = 3 V			NA	μA
V_MID	AV_CC divider at channel 11	ADC12ON = 1, INCH = 0Bh, V_MID is ≉ 0.5 × V_AVCC	V_CC = 2.2 V		1.1	1.1±0.04	V
V_MID	AV_CC divider at channel 11	ADC12ON = 1, INCH = 0Bh, V_MID is ≉ 0.5 × V_AVCC	V_CC = 3 V		1.5	1.5 ±0.04	V
t_VMID(sample)	Sample time required if channel 11 is selected ⁽⁶⁾	ADC12ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB	V_CC = 2.2 V	1400			ns
t_VMID(sample)	Sample time required if channel 11 is selected ⁽⁶⁾	ADC12ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB	V_CC = 3 V	1220			ns

(1) Limits characterized.

(2) The sensor current I_SENSOR is consumed if (ADC12ON = 1 and REFON = 1) or (ADC12ON = 1 and INCH = 0Ah and sample signal is high). When REFON = 1, I_SENSOR is included in I_REF+. When REFON = 0, I_SENSOR applies during conversion of the temperature sensor input (INCH = 0Ah).

(3) The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended to minimize the offset error of the built-in temperature sensor.

(4) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on).

(5) No additional current is needed. The V_MID is used during sampling.

(6) The on-time t_VMID(on) is included in the sampling time t_VMID(sample); no additional on time is needed.

4.53 12-Bit DAC Supply Specifications – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
AV_CC	Supply voltage range	AV_CC = DV_CC, AV_SS = DV_SS = 0 V		2.2		3.6	V
I_DD	Supply current, single DAC channel⁽¹⁾⁽²⁾	DAC12AMPx = 2, DAC12IR = 0, DAC12_xDAT = 0x0800, V_CC = 2.2 V or 3 V	T_A = -55°C to 85°C		50	110	μA
			T_A = 105°C		69	150
		DAC12AMPx = 2, DAC12IR = 1, DAC12_xDAT = 0x0800, V_eREF+ = V_REF+ = AV_CC, V_CC = 2.2 V or 3 V			50	130
		DAC12AMPx = 5, DAC12IR = 1, DAC12_xDAT = 0x0800, V_eREF+ = V_REF+ = AV_CC, V_CC = 2.2 V or 3 V			200	440
		DAC12AMPx = 7, DAC12IR = 1, DAC12_xDAT = 0x0800, V_eREF+ = V_REF+ = AV_CC, V_CC = 2.2 V or 3 V			700	1500
PSSR	Power-supply rejection ratio⁽³⁾⁽⁴⁾	DAC12_xDAT = 800h, V_REF = 1.5 V, ΔAV_CC = 100 mV, V_CC = 2.2 V or 3 V			70		dB
PSSR	Power-supply rejection ratio⁽³⁾⁽⁴⁾	DAC12_xDAT = 800h, V_REF = 1.5 V or 2.5 V, ΔAV_CC = 100 mV, V_CC = 2.2 V or 3 V			70		dB

(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.

(2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Section 4.57.

(3) PSRR = 20 × log{ΔAV_CC/ΔV_{DAC12_xOUT}}

(4) V_REF is applied externally. The internal reference is not used.

4.54 12-Bit DAC Linearity Parameters – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Resolution	12-bit monotonic	12			bits
INL	Integral nonlinearity⁽¹⁾	V_REF = 1.5 V, DAC12AMPx = 7, DAC12IR = 1, V_CC = 2.2 V or 3 V		±2	±8	LSB
INL	Integral nonlinearity⁽¹⁾	V_REF = 2.5 V, DAC12AMPx = 7, DAC12IR = 1, V_CC = 2.2 V or 3 V		±2	±8	LSB
DNL	Differential nonlinearity⁽¹⁾	V_REF = 1.5 V, DAC12AMPx = 7, DAC12IR = 1, V_CC = 2.2 V or 3 V		±0.4	±1	LSB
DNL	Differential nonlinearity⁽¹⁾	V_REF = 2.5 V, DAC12AMPx = 7, DAC12IR = 1, V_CC = 2.2 V or 3 V		±0.4	±1	LSB
E_O	Offset voltage without calibration⁽¹⁾⁽²⁾	V_REF = 1.5 V, DAC12AMPx = 7, DAC12IR = 1, V_CC = 2.2 V or 3 V		±21		LSB
	Offset voltage without calibration⁽¹⁾⁽²⁾	V_REF = 2.5 V, DAC12AMPx = 7, DAC12IR = 1, V_CC = 2.2 V or 3 V		±21
	Offset voltage with calibration⁽¹⁾⁽²⁾	V_REF = 1.5 V, DAC12AMPx = 7, DAC12IR = 1, V_CC = 2.2 V or 3 V			±3.5
	Offset voltage with calibration⁽¹⁾⁽²⁾	V_REF = 2.5 V, DAC12AMPx = 7, DAC12IR = 1, V_CC = 2.2 V or 3 V			±3.5
d_E(O)/d_T	Offset error temperature coefficient⁽¹⁾			30		µV/°C
E_G	Gain error⁽¹⁾	V_REF = 1.5 V, V_CC = 2.2 V or 3 V			±3.5	LSB
E_G	Gain error⁽¹⁾	V_REF = 2.5 V, V_CC = 2.2 V or 3 V			±3.5	LSB
d_E(G)/d_T	Gain temperature coefficient⁽¹⁾			10		ppm of FSR/°C
t_{Offset_Cal}	Time for offset calibration⁽³⁾	DAC12AMPx = 2, V_CC = 2.2 V or 3 V			100	LSB
		DAC12AMPx = 3, 5, V_CC = 2.2 V or 3 V			32
		DAC12AMPx = 4, 6, 7, V_CC = 2.2 V or 3 V			6

(1) Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of the first-order equation: y = a + b × x. V_{DAC12_xOUT} = E_O + (1 + E_G) × (V_eREF+/4095) × DAC12_xDAT, DAC12IR = 1.

(2) The offset calibration works on the output operational amplifier. Offset calibration is triggered setting bit DAC12CALON.

(3) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx={0, 1}.The DAC12 module should be configured prior to initiating calibration. Port activity during calibration may affect accuracy and is not recommended.

MSP430F2619S-HT linearity_test_las697.gif

Figure 4-42 Linearity Test Load Conditions and Gain/Offset Definition

4.55 Typical Characteristics - 12-Bit DAC Linearity Specifications

Figure 4-43 Typical INL Error vs Digital Input Data

Figure 4-44 Typical DNL Error vs Digital Input Data

4.56 12-Bit DAC Output Specifications – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_O	Output voltage range⁽¹⁾ (see Figure 4-45)	No Load, V_eREF+ = AV_CC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7V_CC = 2.2 V or 3 V	0		0.005	V
		No Load, V_eREF+ = AV_CC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7V_CC = 2.2 V or 3 V	AV_CC - 0.05		AV_CC
		R_Load = 3 kΩ, V_eREF+ = AV_CC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7, V_CC = 2.2 V or 3 V	0		0.1
		R_Load = 3 kΩ, V_eREF+ = AV_CC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7, V_CC = 2.2 V or 3 V	AV_CC - 0.13		AV_CC
C_L(DAC12)	Max DAC12 load capacitance	V_CC = 2.2 V or 3 V			100	pF
I_L(DAC12)	Max DAC12 load current	V_CC = 2.2 V	–0.5		0.5	mA
I_L(DAC12)	Max DAC12 load current	V_CC = 3 V	–1		1	mA
R_O/P(DAC12)	Output resistance (see Figure 4-45)	R_Load = 3 kΩ, V_O/P(DAC12) = 0 V, DAC12AMPx = 7, DAC12_xDAT = 0h, V_CC = 2.2 V or 3 V		150	250	Ω
		R_Load = 3 kΩ, V_O/P(DAC12) = 0 V, DAC12AMPx = 7, DAC12_xDAT = 0FFFh, V_CC = 2.2 V or 3 V		150	250
		R_Load = 3 kΩ, 0.3 V ≤ V_O/P(DAC12) ≤ AV_CC - 0.3 V, DAC12AMPx = 7, V_CC = 2.2 V or 3 V		1	4

(1) Data is valid after the offset calibration of the output amplifier.

MSP430F2619S-HT dac12_x_output_las697.gif

Figure 4-45 DAC12_x Output Resistance Tests

4.57 12-Bit DAC Reference Input Specifications – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_eREF+	Reference input voltage range	DAC12IR = 0⁽¹⁾⁽²⁾, V_CC = 2.2 V or 3 V		AV_CC/3	AV_CC + 0.2	V
V_eREF+	Reference input voltage range	DAC12IR = 1⁽³⁾⁽⁴⁾, V_CC = 2.2 V or 3 V		AV_CC	AV_CC + 0.2	V
Ri_(VREF+), Ri_(VeREF+)	Reference input resistance	DAC12_0 IR = DAC12_1 IR = 0, V_CC = 2.2 V or 3 V	20			MΩ
		DAC12_0 IR = 1, DAC12_1 IR = 0, V_CC = 2.2 V or 3 V	40	48	56	kΩ
		DAC12_0 IR = 0, DAC12_1 IR = 1, V_CC = 2.2 V or 3 V	20	24	28
		DAC12_0 IR = 0, DAC12_1 IR = 1 DAC12_0 SREFx = DAC12_1 SREFx⁽⁵⁾, V_CC = 2.2 V or 3 V	20	24	28

(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV_CC).

(2) The maximum voltage applied at reference input voltage terminal V_eREF+ = [AV_CC - V_E(O)] / [3 x (1 + E_G)].

(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV_CC).

(4) The maximum voltage applied at reference input voltage terminal V_eREF+ = [AV_CC - V_E(O)] / (1 + E_G).

(5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance.

4.58 12-Bit DAC Dynamic Specifications, V_REF = V_CC, DAC12IR = 1 – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
t_ON	SR	DAC12_xDAT = 800h, Error_V(O) < ±0.5 LSB⁽¹⁾ (see Figure 4-46), V_CC = 2.2 V or 3 V	DAC12AMPx = 0 → {2, 3, 4}		60	120	μs
			DAC12AMPx = 0 → {5, 6}		15	30
			DAC12AMPx = 0 → 7		6	12
t_S(FS)	Settling time, full scale	DAC12_xDAT = 80h → F7Fh → 80h, V_CC = 2.2 V or 3 V	DAC12AMPx = 2		100	200	μs
			DAC12AMPx = 3, 5		40	80
			DAC12AMPx = 4, 6, 7		15	30
t_S(C-C)	Settling time, code to code	DAC12_xDAT = 3F8h → 408h → 3F8h, V_CC = 2.2 V or 3 V	DAC12AMPx = 2		5		μs
			DAC12AMPx = 3, 5		2
			DAC12AMPx = 4, 6, 7		1
SR	Slew rate⁽²⁾	DAC12_xDAT = 80h → F7Fh → 80h, V_CC = 2.2 V or 3 V	DAC12AMPx = 2	0.05	0.12		V/μs
			DAC12AMPx = 3, 5	0.35	0.7
			DAC12AMPx = 4, 6, 7	1.5	2.7
	Glitch energy, full scale	DAC12_xDAT = 80h → F7Fh → 80h, V_CC = 2.2 V or 3 V	DAC12AMPx = 2		600		nV-s
			DAC12AMPx = 3, 5		150
			DAC12AMPx = 4, 6, 7		30
BW_-3dB	3-dB bandwidth, V_DC = 1.5 V, V_AC = 0.1 V_PP (see Figure 4-48)	DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h, V_CC = 2.2 V or 3 V		40			kHz
		DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h, V_CC = 2.2 V or 3 V		180
		DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h, V_CC = 2.2 V or 3 V		550
	Channel-to-channel crosstalk⁽³⁾ (see Figure 4-49)	DAC12_0DAT = 800h, No load, DAC12_1DAT = 80h ↔ F7Fh, R_Load = 3 kΩ, ƒ_{DAC12_1OUT} = 10 kHz, Duty cycle = 50%, V_CC = 2.2 V or 3 V			–80		dB
	Channel-to-channel crosstalk⁽³⁾ (see Figure 4-49)	DAC12_0DAT = 80h ↔ F7Fh, R_Load = 3 kΩ, DAC12_1DAT = 800h, No load, ƒ_{DAC12_0OUT} = 10 kHz, Duty cycle = 50%, V_CC = 2.2 V or 3 V			–80		dB

(1) R_Load and C_Load are connected to AV_SS (not AV_CC/2) in Figure 4-46.

(2) Slew rate applies to output voltage steps ≥ 200 mV.

(3) R_LOAD = 3 kΩ, C_LOAD = 100 pF

MSP430F2619S-HT settling_time_glitch_las697.gif

Figure 4-46 Settling Time and Glitch Energy Testing

Figure 4-47 Slew Rate Testing

MSP430F2619S-HT test_cond_3db_las697.gif

Figure 4-48 Test Conditions for 3-dB Bandwidth Specification

Figure 4-49 Crosstalk Test Conditions

4.59 Flash Memory – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_{CC(PGM/ERASE)}	Program and erase supply voltage		2.2		3.6	V
ƒ_FTG	Flash timing generator frequency		257		476	kHz
I_PGM	Supply current from V_CC during program	V_CC = 2.2 or 3.6 V		3	5	mA
I_ERASE	Supply current from V_CC during erase	V_CC = 2.2 or 3.6 V		3	7	mA
t_CPT	Cumulative program time	See ⁽¹⁾, V_CC = 2.2 or 3.6 V			10	ms
t_CMErase	Cumulative mass erase time	V_CC = 2.2 or 3.6 V	20			ms
	Program/Erase endurance		10⁴	10⁵		cycles
t_Retention	Data retention duration	T_J = 25°C	100			years
t_Word	Word or byte program time	See⁽²⁾		35		t_FTG
t_{Block, 0}	Block program time for 1^st byte or word	See⁽²⁾		30		t_FTG
t_{Block, 1-63}	Block program time for each additional byte or word	See⁽²⁾		21		t_FTG
t_{Block, End}	Block program end-sequence wait time	See⁽²⁾		6		t_FTG
t_{Mass Erase}	Mass erase time	See⁽²⁾		10593		t_FTG
t_{Seg Erase}	Segment erase time	See⁽²⁾		4819		t_FTG

(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes.

(2) These values are hardwired into the Flash Controller's state machine (t_FTG = 1/ƒ_FTG).

Figure 4-50 Flash Data Retention vs Junction Temperature

4.60 RAM – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_(RAMh)	RAM retention supply voltage ⁽¹⁾	CPU halted	1.6		V

(1) This parameter defines the minimum supply voltage V_CC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition.

4.61 JTAG and Spy-Bi-Wire Interface – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ƒ_TCK	TCK input frequency	See ⁽¹⁾	V_CC = 2.2 V	0		5	MHz
ƒ_TCK	TCK input frequency	See ⁽¹⁾	V_CC = 3 V	0		10	MHz
R_Internal	Internal pulldown resistance on TEST	See ⁽²⁾, V_CC = 2.2 V or 3 V		25	60	90	kΩ

(1) ƒ_TCK may be restricted to meet the timing requirements of the module selected.

(2) TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.

4.62 JTAG Fuse⁽¹⁾ – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_CC(FB)	Supply voltage during fuse-blow condition	T_A = 25°C	2.5		V
V_FB	Voltage level on TEST for fuse blow		6	7	V
I_FB	Supply current into TEST during fuse blow			100	mA
t_FB	Time to blow fuse			1	ms

(1) Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode.

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4 Specifications

4.1 Absolute Maximum Ratings(1)

4.2 ESD Ratings

4.3 Recommended Operating Conditions(1)(3)

4.4 Thermal Information

4.5 Active-Mode Supply Current Into AVCC Excluding External Current – Electrical Characteristics(1)(2)

4.6 Typical Characteristics – Active-Mode Supply Current (Into DVCC + AVCC)

4.7 Active-Mode Current vs DCO Frequency

4.8 Low-Power-Mode Supply Currents Into AVCC Excluding External Current – Electrical Characteristics(1)(2)

4.9 Typical Characteristics – LPM4 Current

4.10 Schmitt-Trigger Inputs (Ports P1 Through P6, and RST/NMI, JTAG, XIN, and XT2IN)(1) – Electrical Characteristics

4.11 Inputs (Ports P1 and P2) – Electrical Characteristics

4.12 Leakage Current (Ports P1 Through P6) – Electrical Characteristics

4.13 Standard Inputs - RST/NMI – Electrical Characteristics

4.14 Outputs (Ports P1 Through P6) – Electrical Characteristics

4.15 Output Frequency (Ports P1 Through P6) – Electrical Characteristics

4.16 Typical Characteristics – Outputs

4.17 POR/Brownout Reset (BOR) – Electrical Characteristics(1)(2)

4.18 Typical Characteristics - POR/Brownout Reset (BOR)

4.19 SVS (Supply Voltage Supervisor/Monitor) - Electrical Characteristics

4.20 Typical Characteristics - SVS

4.21 Main DCO Characteristics

4.22 DCO Frequency – Electrical Characteristics

4.23 Calibrated DCO Frequencies (Tolerance at Calibration) – Electrical Characteristics

4.24 Calibrated DCO Frequencies (Tolerance Over Temperature) – Electrical Characteristics

4.25 Calibrated DCO Frequencies (Tolerance Over Supply Voltage VCC) – Electrical Characteristics

4.26 Calibrated DCO Frequencies (Overall Tolerance) – Electrical Characteristics

4.27 Typical Characteristics – Calibrated DCO Frequency

4.28 Wake-Up From Low-Power Modes (LPM3/4) – Electrical Characteristics

4.29 Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4

4.30 DCO With External Resistor ROSC – Electrical Characteristics(1)

4.31 Typical Characteristics - DCO With External Resistor ROSC

4.32 Crystal Oscillator (LFXT1) Low-Frequency Modes – Electrical Characteristics(1)(2)

4.33 Internal Very-Low-Power, Low-Frequency Oscillator (VLO) – Electrical Characteristics

4.34 Crystal Oscillator (LFXT1) High Frequency Modes – Electrical Characteristics(5)

4.35 Typical Characteristics – LFXT1 Oscillator in HF Mode (XTS = 1)

4.36 Crystal Oscillator (XT2) – Electrical Characteristics(5)

4.37 Typical Characteristics – XT2 Oscillator

4.38 Timer_A – Electrical Characteristics

4.39 Timer_B – Electrical Characteristics

4.40 USCI (UART Mode) – Electrical Characteristics

4.41 USCI (SPI Master Mode) – Electrical Characteristics

4.42 USCI (SPI Slave Mode) – Electrical Characteristics

4.43 USCI (I2C Mode) – Electrical Characteristics

4.44 Comparator_A+ – Electrical Characteristics(1)

4.45 Typical Characteristics – Comparator A+

4.46 12-Bit ADC Power-Supply and Input Range Conditions – Electrical Characteristics(1)

4.47 12-Bit ADC External Reference – Electrical Characteristics

4.48 12-Bit ADC Built-In Reference – Electrical Characteristics

4.49 Typical Characteristics – ADC12

4.50 12-Bit ADC Timing Parameters – Electrical Characteristics

4.51 12-Bit ADC Linearity Parameters – Electrical Characteristics

4.52 12-Bit ADC Temperature Sensor and Built-In VMID – Electrical Characteristics

4.53 12-Bit DAC Supply Specifications – Electrical Characteristics

4.54 12-Bit DAC Linearity Parameters – Electrical Characteristics

4.55 Typical Characteristics - 12-Bit DAC Linearity Specifications

4.56 12-Bit DAC Output Specifications – Electrical Characteristics

4.57 12-Bit DAC Reference Input Specifications – Electrical Characteristics

4.58 12-Bit DAC Dynamic Specifications, VREF = VCC, DAC12IR = 1 – Electrical Characteristics

4.59 Flash Memory – Electrical Characteristics

4.60 RAM – Electrical Characteristics

4.61 JTAG and Spy-Bi-Wire Interface – Electrical Characteristics

4.62 JTAG Fuse(1) – Electrical Characteristics

4.1 Absolute Maximum Ratings⁽¹⁾

4.3 Recommended Operating Conditions⁽¹⁾⁽³⁾

4.5 Active-Mode Supply Current Into AV_CC Excluding External Current –
Electrical Characteristics⁽¹⁾⁽²⁾

4.6 Typical Characteristics – Active-Mode Supply Current (Into DV_CC+ AV_CC)

4.8 Low-Power-Mode Supply Currents Into AV_CC Excluding External Current – Electrical Characteristics⁽¹⁾⁽²⁾

4.10 Schmitt-Trigger Inputs (Ports P1 Through P6, and RST/NMI, JTAG, XIN, and XT2IN)⁽¹⁾ – Electrical Characteristics

4.17 POR/Brownout Reset (BOR) – Electrical Characteristics⁽¹⁾⁽²⁾

4.25 Calibrated DCO Frequencies (Tolerance Over Supply Voltage V_CC) – Electrical Characteristics

4.30 DCO With External Resistor R_OSC – Electrical Characteristics⁽¹⁾

4.31 Typical Characteristics - DCO With External Resistor R_OSC

4.32 Crystal Oscillator (LFXT1) Low-Frequency Modes – Electrical Characteristics⁽¹⁾⁽²⁾

4.34 Crystal Oscillator (LFXT1) High Frequency Modes – Electrical Characteristics⁽⁵⁾

4.36 Crystal Oscillator (XT2) – Electrical Characteristics⁽⁵⁾

4.44 Comparator_A+ – Electrical Characteristics⁽¹⁾

4.46 12-Bit ADC Power-Supply and Input Range Conditions – Electrical Characteristics⁽¹⁾

4.52 12-Bit ADC Temperature Sensor and Built-In V_MID – Electrical Characteristics

4.58 12-Bit DAC Dynamic Specifications, V_REF = V_CC, DAC12IR = 1 – Electrical Characteristics

4.62 JTAG Fuse⁽¹⁾ – Electrical Characteristics