LPV521 纳瓦级功率、1.8V、RRIO、CMOS 输入运算放大器 | 德州仪器 TI.com.cn

LPV521
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纳瓦级功率、1.8V、RRIO、CMOS 输入运算放大器

纳瓦级功率、1.8V、RRIO、CMOS 输入运算放大器 - LPV521
数据表
 

描述

The LPV521 is a single nanopower 552-nW amplifier designed for ultra long life battery applications. The operating voltage range of 1.6 V to 5.5 V coupled with typically 351 nA of supply current make it well suited for RFID readers and remote sensor nanopower applications. The device has input common mode voltage 0.1 V over the rails, guaranteed TCVOS and voltage swing to the rail output performance. The LPV521 has a carefully designed CMOS input stage that outperforms competitors with typically 40 fA IBIAS currents. This low input current significantly reduces IBIAS and IOS errors introduced in megohm resistance, high impedance photodiode, and charge sense situations. The LPV521 is a member of the PowerWise family and has an exceptional power-to-performance ratio.

The wide input common mode voltage range, guaranteed 1 mV VOS and 3.5 µV/°C TCVOS enables accurate and stable measurement for both high-side and low-side current sensing.

EMI protection was designed into the device to reduce sensitivity to unwanted RF signals from cell phones or other RFID readers.

The LPV521 is offered in the 5-pin SC70 package.

特性

  • For VS = 5 V, Typical Unless Otherwise Noted
    • Supply Current at VCM = 0.3 V 400 nA (Max)
    • Operating Voltage Range 1.6 V to 5.5 V
    • Low TCVOS 3.5 µV/°C (Max)
    • VOS 1 mV (Max)
    • Input Bias Current 40 fA
    • PSRR 109 dB
    • CMRR 102 dB
    • Open-Loop Gain 132 dB
    • Gain Bandwidth Product 6.2 kHz
    • Slew Rate 2.4 V/ms
    • Input Voltage Noise at f = 100 Hz 255 nV/√Hz
    • Temperature Range –40°C to 125°C

参数

与其它产品相比 通用 运算放大器 邮件 下载到电子表格中
Part number 立即下单 Number of channels (#) Total supply voltage (Min) (+5V=5, +/-5V=10) Total supply voltage (Max) (+5V=5, +/-5V=10) GBW (Typ) (MHz) Slew rate (Typ) (V/us) Rail-to-rail Vos (offset voltage @ 25 C) (Max) (mV) Iq per channel (Typ) (mA) Vn at 1 kHz (Typ) (nV/rtHz) Rating Operating temperature range (C) Package Group Package size: mm2:W x L (PKG) Offset drift (Typ) (uV/C) Features Input bias current (Max) (pA) CMRR (Typ) (dB) Output current (Typ) (mA) Architecture
LPV521 立即下单 1     1.6     5.5     0.0062     0.0024     In
Out    
1     0.000351     255     Catalog     -40 to 125     SC70 | 5     5SC70: 4 mm2: 2.1 x 2 (SC70 | 5)     0.4     EMI Hardened     1     102     22     CMOS    
LPV542 立即下单 2     1.6     5.5     0.008     0.0037     In
Out    
3     0.00048     250     Catalog     -40 to 125     VSSOP | 8
X1SON | 8    
8VSSOP: 15 mm2: 4.9 x 3 (VSSOP | 8)
8X1SON: 9 mm2: 3 x 3 (X1SON | 8)    
1     EMI Hardened     1     101     30      
TLV521 立即下单 1     1.7     5.5     0.006     0.0029     In
Out    
3     0.00035     300     Catalog     -40 to 125     SC70 | 5     5SC70: 4 mm2: 2.1 x 2 (SC70 | 5)     1.5     Cost Optimized
EMI Hardened    
  100     12     CMOS    
TLV522 立即下单 2     1.7     5.5     0.008     0.0037     In
Out    
4     0.0005     300     Catalog     -40 to 125     VSSOP | 8     8VSSOP: 15 mm2: 4.9 x 3 (VSSOP | 8)     1.5     Cost Optimized
EMI Hardened    
  90     5     CMOS