LPC660 低功耗 CMOS 四路运算放大器 | 德州仪器 TI.com.cn

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低功耗 CMOS 四路运算放大器

低功耗 CMOS 四路运算放大器 - LPC660


The LPC660 CMOS Quad operational amplifier is ideal for operation from a single supply. It features a wide range of operating voltages from +5V to +15V and features rail-to-rail output swing in addition to an input common-mode range that includes ground. Performance limitations that have plagued CMOS amplifiers in the past are not a problem with this design. Input VOS, drift, and broadband noise as well as voltage gain (into 100 kΩ and 5 kΩ) are all equal to or better than widely accepted bipolar equivalents, while the power supply requirement is typically less than 1 mW.

This chip is built with National's advanced Double-Poly Silicon-Gate CMOS process.

See the LPC662 datasheet for a Dual CMOS operational amplifier and LPC661 datasheet for a single CMOS operational amplifier with these same features.


  • Rail-to-rail output swing
  • Micropower operation: (1 mW)
  • Specified for 100 kΩ and 5 kΩ loads
  • High voltage gain: 120 dB
  • Low input offset voltage: 3 mV
  • Low offset voltage drift: 1.3 μV/°C
  • Ultra low input bias current: 2 fA
  • Input common-mode includes V
  • Operation range from +5V to +15V
  • Low distortion: 0.01% at 1 kHz
  • Slew rate: 0.11 V/μs
  • Full military temp. range available

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Part number 立即下单 Number of channels (#) Total supply voltage (Min) (+5V=5, +/-5V=10) Total supply voltage (Max) (+5V=5, +/-5V=10) GBW (Typ) (MHz) Slew rate (Typ) (V/us) Rail-to-rail Vos (offset voltage @ 25 C) (Max) (mV) Iq per channel (Typ) (mA) Vn at 1 kHz (Typ) (nV/rtHz) Rating Operating temperature range (C) Package Group Package size: mm2:W x L (PKG) Offset drift (Typ) (uV/C) Features Input bias current (Max) (pA) CMRR (Typ) (dB) Output current (Typ) (mA) Architecture
LPC660 立即下单 4     5     15     0.35     0.11     In to V-
3     0.04     42     Catalog     -40 to 85     SOIC | 14     14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)     1.3         20     83     21     CMOS