ZHCSGT4 September 2017 LP87332A-Q1

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6I2C Serial Bus Timing Parameters
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 DC-DC Converters
        1. 7.3.1.1Overview
        2. 7.3.1.2Transition Between PWM and PFM Modes
        3. 7.3.1.3Buck Converter Load Current Measurement
        4. 7.3.1.4Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4 Power-Up
      5. 7.3.5 Regulator Control
        1. 7.3.5.1Enabling and Disabling Regulators
        2. 7.3.5.2Changing Output Voltage
      6. 7.3.6 Enable and Disable Sequences
      7. 7.3.7 Device Reset Scenarios
      8. 7.3.8 Diagnosis and Protection Features
        1. 7.3.8.1Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1PGOOD Pin Gated mode
          2. 7.3.8.1.2PGOOD Pin Continuous Mode
        2. 7.3.8.2Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1Output Power Limit
          2. 7.3.8.2.2Thermal Warning
        3. 7.3.8.3Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2Overvoltage Protection
          3. 7.3.8.3.3Thermal Shutdown
        4. 7.3.8.4Fault (Power Down)
          1. 7.3.8.4.1Undervoltage Lockout
      9. 7.3.9 Operation of the GPO Signals
      10. 7.3.10Digital Signal Filtering
    4. 7.4Device Functional Modes
      1. 7.4.1Modes of Operation
    5. 7.5Programming
      1. 7.5.1I2C-Compatible Interface
        1. 7.5.1.1Data Validity
        2. 7.5.1.2Start and Stop Conditions
        3. 7.5.1.3Transferring Data
        4. 7.5.1.4I2C-Compatible Chip Address
        5. 7.5.1.5Auto-Increment Feature
    6. 7.6Register Maps
      1. 7.6.1Register Descriptions
        1. 7.6.1.1 DEV_REV
        2. 7.6.1.2 OTP_REV
        3. 7.6.1.3 BUCK0_CTRL_1
        4. 7.6.1.4 BUCK0_CTRL_2
        5. 7.6.1.5 BUCK1_CTRL_1
        6. 7.6.1.6 BUCK1_CTRL_2
        7. 7.6.1.7 BUCK0_VOUT
        8. 7.6.1.8 BUCK1_VOUT
        9. 7.6.1.9 LDO0_CTRL
        10. 7.6.1.10LDO1_CTRL
        11. 7.6.1.11LDO0_VOUT
        12. 7.6.1.12LDO1_VOUT
        13. 7.6.1.13BUCK0_DELAY
        14. 7.6.1.14BUCK1_DELAY
        15. 7.6.1.15LDO0_DELAY
        16. 7.6.1.16LDO1_DELAY
        17. 7.6.1.17GPO_DELAY
        18. 7.6.1.18GPO2_DELAY
        19. 7.6.1.19GPO_CTRL
        20. 7.6.1.20CONFIG
        21. 7.6.1.21PLL_CTRL
        22. 7.6.1.22PGOOD_CTRL_1
        23. 7.6.1.23PGOOD_CTRL_2
        24. 7.6.1.24PG_FAULT
        25. 7.6.1.25RESET
        26. 7.6.1.26INT_TOP_1
        27. 7.6.1.27INT_TOP_2
        28. 7.6.1.28INT_BUCK
        29. 7.6.1.29INT_LDO
        30. 7.6.1.30TOP_STAT
        31. 7.6.1.31BUCK_STAT
        32. 7.6.1.32LDO_STAT
        33. 7.6.1.33TOP_MASK_1
        34. 7.6.1.34TOP_MASK_2
        35. 7.6.1.35BUCK_MASK
        36. 7.6.1.36LDO_MASK
        37. 7.6.1.37SEL_I_LOAD
        38. 7.6.1.38I_LOAD_2
        39. 7.6.1.39I_LOAD_1
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
        1. 8.2.1.1Inductor Selection
        2. 8.2.1.2Buck Input Capacitor Selection
        3. 8.2.1.3Buck Output Capacitor Selection
        4. 8.2.1.4LDO Input Capacitor Selection
        5. 8.2.1.5LDO Output Capacitor Selection
      2. 8.2.2Detailed Design Procedure
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11器件和文档支持
    1. 11.1器件支持
      1. 11.1.1Third-Party Products Disclaimer
    2. 11.2接收文档更新通知
    3. 11.3社区资源
    4. 11.4商标
    5. 11.5静电放电警告
    6. 11.6Glossary
  12. 12机械、封装和可订购信息

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The LP87332A-Q1 is a power management unit including two step-down regulators, two linear regulators, and two general-purpose digital output signals.

Typical Application

LP87332A-Q1 Appl_schem_SNVSAB5.gif Figure 25. LP87332A-Q1 Typical Application

Design Requirements

Inductor Selection

The inductors L0 and L1 are shown in the Typical Application. The inductance and DCR of the inductor affects the control loop of the buck regulator. TI recommends using inductors similar to those listed in Table 8. Pay attention to the saturation current and temperature rise current of the inductor. Check that the saturation current is higher than the peak current limit and the temperature rise current is higher than the maximum expected rms output current. Minimum effective inductance to ensure good performance is 0.22 μH at maximum peak output current over the operating temperature range. DC resistance of the inductor must be less than 0.05 Ω for good efficiency at high-current condition. The inductor AC loss also affects conversion efficiency. Higher Q factor at switching frequency usually gives better efficiency at light load to middle load. Shielded inductors are preferred as they radiate less noise.

Table 8. Recommended Inductors

MANUFACTURERPART NUMBERVALUEDIMENSIONS L × W × H (mm)RATED DC CURRENT
ISAT maximum (typical) /
ITEMP maximum (typical) (A)
DCR
typical / maximum (mΩ)
TOKODFE252012PD-R47M0.47 µH (20%)2.5 × 2 × 1.25.2 (–) / 4 (–)(1)— / 27
Tayo YudenMDMK2020TR47MMV0.47 µH (20%)2 × 2 ×1.24.2 (4.8) / 2.3 (2.45)40 / 46
Operating temperature range is up to 125°C including self temperature rise.

Buck Input Capacitor Selection

The input capacitors CIN_BUCK0 and CIN_BUCK1 are shown in the Typical Application. A ceramic input bypass capacitor of 10 μF is required for each phase of the regulator. Place the input capacitor as close as possible to the VIN_Bx pin and PGND_Bx pin of the device. A larger value or higher voltage rating improves the input voltage filtering. Use X7R type of capacitors, not Y5V or F. Also the DC bias characteristics capacitors must be considered. Minimum effective input capacitance to ensure good performance is 1.9 μF per buck input at maximum input voltage including tolerances, ambient temperature range and aging. This is assuming that there are at least 22 μF of additional capacitance common for all the power input pins on the system power rail. See Table 9.

The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient ripple current rating. In addition ferrite can be used in front of the input capacitor to reduce the EMI.

Table 9. Recommended Buck Input Capacitor (X7R Dielectric)

MANUFACTURERPART NUMBERVALUECASE SIZEDIMENSIONS L × W × H (mm)VOLTAGE RATING
MurataGCM21BR71A106KE2210 µF (10%)08052 × 1.25 × 1.2510 V

Buck Output Capacitor Selection

The output capacitor COUT_BUCK0 and COUT_BUCK1 are shown in Typical Application. A ceramic local output capacitor of 22 μF is required per phase. Use ceramic capacitors, X7R type; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance to ensure good performance is 10 μF per phase including the DC voltage roll-off, tolerances, aging, and temperature effects.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. See Table 10.

POL capacitors can be used to improve load transient performance and to decrease the ripple voltage. A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as decreases the PFM switching frequency. However, output capacitance higher than 150 μF per phase is not necessarily of any benefit. Note that the output capacitor may be the limiting factor in the output voltage ramp, see Specifications for maximum output capacitance for different slew-rate settings. For large output capacitors, the output voltage might be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be longer. At shutdown the output voltage is discharged to 0.6 V level using forced-PWM operation. This can increase the input voltage if the load current is small and the output capacitor is large compared to input capacitor. Below 0.6 V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant.

Table 10. Recommended Buck Output Capacitors (X7R Dielectric)

MANUFACTURERPART NUMBERVALUECASE SIZEDIMENSIONS L × W × H (mm)VOLTAGE RATING
MurataGCM31CR71A226KE0222 µF (10%)12063.2 × 1.6 × 1.610 V

LDO Input Capacitor Selection

The input capacitors CIN_LDO0 and CIN_LDO1 are shown in the Figure 25. A ceramic input capacitor of 2.2 μF, 6.3 V is sufficient for most applications. Place the input capacitor as close as possible to the VIN_LDOx pin and AGND pin of the device. A larger value or higher voltage rating improves the input voltage filtering. Use X7R type of capacitors, not Y5V or F. DC bias characteristics of capacitors must be considered, minimum effective input capacitance to ensure good performance is 0.6 μF per LDO input at maximum input voltage including tolerances, ambient temperature range and aging. See Table 11.

Table 11. Recommended LDO Input Capacitors (X7R Dielectric)

MANUFACTURERPART NUMBERVALUECASE SIZEDIMENSIONS L × W × H (mm)VOLTAGE RATING
MurataGCM188R70J225KE222.2 µF (10%)06031.6 × 0.8 × 0.86.3 V
MurataGCM21BR71C475KA734.7 µF (10%)08052 × 1.25 × 1.2516 V

LDO Output Capacitor Selection

The output capacitors COUT_LDO0 and COUT_LDO1 are shown in the Typical Application. A ceramic output capacitor of minimum 1.0 μF is required. Place the output capacitor as close to the VOUT_LDOx pin and AGND pin of the device as possible. Use X7R type of capacitors, not Y5V or F. DC bias characteristics of capacitors must be considered, minimum effective output capacitance to ensure good performance is 0.4 μF per LDO input at maximum input voltage including tolerances, ambient temperature range and aging. See Table 12.

The output capacitance must be smaller than the input capacitance in order to ensure the stability of the LDO. With a 1-μF output capacitor it is recommended to use at least 2.2-μF input capacitor; with a 2.2-μF output capacitor at least 4.7-μF input capacitance.

The VANA input is used to supply analog and digital circuits in the device. See Table 13 for recommended components from for VANA input supply filtering.

Table 12. Recommended LDO Output Capacitors (X7R Dielectric)

MANUFACTURERPART NUMBERVALUECASE SIZEDIMENSIONS L × W × H (mm)VOLTAGE RATING
MurataGCM188R71C105KA641 µF (10%)06031.6 × 0.8 × 0.816 V
MurataGCM188R70J225KE222.2 µF (10%)06031.6 × 0.8 × 0.86.3 V

Table 13. Recommended Supply Filtering Components

MANUFACTURERPART NUMBERVALUECASE SIZEDIMENSIONS L × W × H (mm)VOLTAGE RATING
MurataGCM155R71C104KA55100 nF (10%)04021 × 0.5 × 0.516 V
MurataGCM188R71C104KA37100 nF (10%)06031.6 × 0.8 × 0.816 V

Detailed Design Procedure

The performance of the LP87332A-Q1 device depends greatly on the care taken in designing the printed circuit board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended, while proper grounding is crucial. Attention must be given to decoupling the power supplies. Decoupling capacitors must be connected close to the device and between the power and ground pins to support high peak currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and output traces as short as possible, because trace inductance, resistance, and capacitance can easily become the performance limiting items. The separate buck regulator power pins VIN_Bx are not connected together internally. Connect the VIN_Bx power connections together outside the package using power plane construction.

Application Curves

Unless otherwise specified: V(VIN_Bx) = V(VIN_LDOx) = V(VANA) = 3.7 V, VOUT_Bx = 1 V, VOUT_LDOx = 1 V, TA = 25°C, L = 0.47 µH (TOKO DFE252012PD-R47M), COUT_BUCK = 22 µF, and CPOL_BUCK = 22 µF, COUT_LDO = 1 µF. Measurements are done using connections in the Figure 25.

LP87332A-Q1 D003_SNVSAB5.gif
VOUT = 1.8 V
Figure 26. Buck Efficiency in PFM/PWM and Forced PWM Mode
LP87332A-Q1 D011_SNVSAB5.gif
VIN = 5 V
Figure 28. Buck Efficiency in Forced PWM Mode
LP87332A-Q1 D019_SNVSAB5.gif
Figure 30. Buck Output Voltage vs Load Current in PFM/PWM Mode
LP87332A-Q1 D023_SNVSAB5.gif
Load = 1 A (PWM) and 0.1 A (PFM)
Figure 32. Buck Output Voltage vs Temperature
LP87332A-Q1 SNVSAB5_D028.png
RLOAD = 1 ΩSlew-rate = 10 mV/µs
Figure 34. Buck Startup with EN1, Forced PWM Mode
LP87332A-Q1 SNVSAB5_D032.png
IOUT = 10 mA
Figure 36. Buck Output Voltage Ripple, PFM Mode
LP87332A-Q1 SNVSAB5_D036.png
Figure 38. Buck Transient from PFM-to-PWM Mode
LP87332A-Q1 SNVSAB5_D042.png
IOUT = 0.1 A → 2 A → 0.1 ATR = TF = 400 ns
Figure 40. Buck Transient Load Step Response, AUTO Mode
LP87332A-Q1 SNVSAB5_D046.gif
Figure 42. Buck VOUT Transition from 0.6 V to 1.4 V With Different Slew Rate Settings
LP87332A-Q1 SNVSAB5_D048.png
Figure 44. Buck Start-up With Short on Output
LP87332A-Q1 D051_SNVSAB5.gif
VOUT = 1 VLoad = 200 mA
Figure 46. LDO Output Voltage vs Input Voltage
LP87332A-Q1 SNVSAB5_D053.png
ILOAD = 0 A
Figure 48. LDO Start-Up
LP87332A-Q1 SNVSAB5_D055.png
ILOAD = 0 A
Figure 50. LDO Shutdown
LP87332A-Q1 SNVSAB5_D057.png
Figure 52. LDO VOUT Transition from 1.8 V to 1.2 V
LP87332A-Q1 SNVSAB5_D059.png
Start-up delay is 500 µs
Figure 54. LDO Start-Up With Short on Output
LP87332A-Q1 D007_SNVSAB5.gif
VIN = 3.3 V
Figure 27. Buck Efficiency in Forced PWM Mode
LP87332A-Q1 D015_SNVSAB5.gif
VOUT = 1 V
Figure 29. Buck Output Voltage vs Load Current in Forced PWM Mode
LP87332A-Q1 D021_SNVSAB5.gif
VOUT = 1 VLoad = 1 A
Figure 31. Buck Output Voltage vs Input Voltage in PWM Mode
LP87332A-Q1 SNVSAB5_D026.png
ILOAD = 0 ASlew-rate = 10 mV/µs
Figure 33. Buck Start-Up With EN1, Forced PWM Mode
LP87332A-Q1 SNVSAB5_D030.png
RLOAD = 1 ΩSlew-rate = 10 mV/µs
Figure 35. Buck Shutdown With EN1, Forced PWM Mode
LP87332A-Q1 SNVSAB5_D034.png
IOUT = 200 mA
Figure 37. Buck Output Voltage Ripple,
Forced PWM Mode
LP87332A-Q1 SNVSAB5_D038.png
Figure 39. Buck Transient from PWM-to-PFM Mode
LP87332A-Q1 SNVSAB5_D044.png
IOUT = 0.1 A → 2 A → 0.1 ATR = TF = 400 ns
Figure 41. Buck Transient Load Step Response, Forced PWM Mode
LP87332A-Q1 SNVSAB5_D047.gif
Figure 43. Buck VOUT Transition from 1.4 V to 0.6 V With Different Slew Rate Settings
LP87332A-Q1 D050_SNVSAB5.gif
VOUT = 1 V
Figure 45. LDO Output Voltage vs Load Current
LP87332A-Q1 D052_SNVSAB5.gif
VOUT = 1 VLoad = 200 mA
Figure 47. LDO Output Voltage vs Temperature
LP87332A-Q1 SNVSAB5_D054.png
RLOAD = 3.3 Ω
Figure 49. LDO Start-Up
LP87332A-Q1 SNVSAB5_D056.png
IOUT = 0 A → 0.3 A → 0 ATR = TF = 1 µs
Figure 51. LDO Transient Load Step Response
LP87332A-Q1 SNVSAB5_D058.png
Figure 53. LDO VOUT Transition from 1.2 V to 1.8 V