ZHCSGT4 September 2017 LP87332A-Q1

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6I2C Serial Bus Timing Parameters
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 DC-DC Converters
        1. 7.3.1.1Overview
        2. 7.3.1.2Transition Between PWM and PFM Modes
        3. 7.3.1.3Buck Converter Load Current Measurement
        4. 7.3.1.4Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4 Power-Up
      5. 7.3.5 Regulator Control
        1. 7.3.5.1Enabling and Disabling Regulators
        2. 7.3.5.2Changing Output Voltage
      6. 7.3.6 Enable and Disable Sequences
      7. 7.3.7 Device Reset Scenarios
      8. 7.3.8 Diagnosis and Protection Features
        1. 7.3.8.1Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1PGOOD Pin Gated mode
          2. 7.3.8.1.2PGOOD Pin Continuous Mode
        2. 7.3.8.2Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1Output Power Limit
          2. 7.3.8.2.2Thermal Warning
        3. 7.3.8.3Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2Overvoltage Protection
          3. 7.3.8.3.3Thermal Shutdown
        4. 7.3.8.4Fault (Power Down)
          1. 7.3.8.4.1Undervoltage Lockout
      9. 7.3.9 Operation of the GPO Signals
      10. 7.3.10Digital Signal Filtering
    4. 7.4Device Functional Modes
      1. 7.4.1Modes of Operation
    5. 7.5Programming
      1. 7.5.1I2C-Compatible Interface
        1. 7.5.1.1Data Validity
        2. 7.5.1.2Start and Stop Conditions
        3. 7.5.1.3Transferring Data
        4. 7.5.1.4I2C-Compatible Chip Address
        5. 7.5.1.5Auto-Increment Feature
    6. 7.6Register Maps
      1. 7.6.1Register Descriptions
        1. 7.6.1.1 DEV_REV
        2. 7.6.1.2 OTP_REV
        3. 7.6.1.3 BUCK0_CTRL_1
        4. 7.6.1.4 BUCK0_CTRL_2
        5. 7.6.1.5 BUCK1_CTRL_1
        6. 7.6.1.6 BUCK1_CTRL_2
        7. 7.6.1.7 BUCK0_VOUT
        8. 7.6.1.8 BUCK1_VOUT
        9. 7.6.1.9 LDO0_CTRL
        10. 7.6.1.10LDO1_CTRL
        11. 7.6.1.11LDO0_VOUT
        12. 7.6.1.12LDO1_VOUT
        13. 7.6.1.13BUCK0_DELAY
        14. 7.6.1.14BUCK1_DELAY
        15. 7.6.1.15LDO0_DELAY
        16. 7.6.1.16LDO1_DELAY
        17. 7.6.1.17GPO_DELAY
        18. 7.6.1.18GPO2_DELAY
        19. 7.6.1.19GPO_CTRL
        20. 7.6.1.20CONFIG
        21. 7.6.1.21PLL_CTRL
        22. 7.6.1.22PGOOD_CTRL_1
        23. 7.6.1.23PGOOD_CTRL_2
        24. 7.6.1.24PG_FAULT
        25. 7.6.1.25RESET
        26. 7.6.1.26INT_TOP_1
        27. 7.6.1.27INT_TOP_2
        28. 7.6.1.28INT_BUCK
        29. 7.6.1.29INT_LDO
        30. 7.6.1.30TOP_STAT
        31. 7.6.1.31BUCK_STAT
        32. 7.6.1.32LDO_STAT
        33. 7.6.1.33TOP_MASK_1
        34. 7.6.1.34TOP_MASK_2
        35. 7.6.1.35BUCK_MASK
        36. 7.6.1.36LDO_MASK
        37. 7.6.1.37SEL_I_LOAD
        38. 7.6.1.38I_LOAD_2
        39. 7.6.1.39I_LOAD_1
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
        1. 8.2.1.1Inductor Selection
        2. 8.2.1.2Buck Input Capacitor Selection
        3. 8.2.1.3Buck Output Capacitor Selection
        4. 8.2.1.4LDO Input Capacitor Selection
        5. 8.2.1.5LDO Output Capacitor Selection
      2. 8.2.2Detailed Design Procedure
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11器件和文档支持
    1. 11.1器件支持
      1. 11.1.1Third-Party Products Disclaimer
    2. 11.2接收文档更新通知
    3. 11.3社区资源
    4. 11.4商标
    5. 11.5静电放电警告
    6. 11.6Glossary
  12. 12机械、封装和可订购信息

Detailed Description

Overview

The LP87332A-Q1 is a high-efficiency, high-performance flexible power supply device with two step-down DC-DC converter cores (Buck0 and Buck1) and two low-dropout (LDO) linear regulators (LDO0 and LDO1) for automotive applications. Table 1 lists the output characteristics of the regulators.

Table 1. Supply Specification

SUPPLYOUTPUT
VOUT RANGE (V)RESOLUTION (mV)IMAX MAXIMUM OUTPUT CURRENT (mA)
Buck00.7 to 3.3610 (0.7 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
3000
Buck10.7 to 3.3610 (0.7 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
3000
LDO00.8 to 3.3100300
LDO10.8 to 3.3100300

The LP87332A-Q1 also supports switching clock synchronization to an external clock (CLKIN pin). The nominal frequency of the external clock can be from 1 MHz to 24 MHz with 1-MHz steps.

Additional features include:

  • Soft-start
  • Input voltage protection:
    • Undervoltage lockout
    • Overvoltage protection
  • Output voltage monitoring and protection:
    • Overvoltage monitoring
    • Undervoltage monitoring
    • Overload protection
  • Thermal warning
  • Thermal shutdown

The LP87332A-Q1 has one dedicated general purpose digital output (GPO) signal. CLKIN pin can be programmed as a second GPO signal (GPO2) if external clock is not needed. The output type (open-drain or push-pull) is programmable for the GPOs.

Functional Block Diagram

LP87332A-Q1 Block_Diagram.gif

Feature Description

DC-DC Converters

Overview

The LP87332A-Q1 includes two step-down DC-DC converter cores. The cores are designed for flexibility; most of the functions are programmable, thus giving a possibility to optimize the regulator operation for each application. The buck regulators deliver 0.7-V to 3.36-V regulated voltage rails from a 2.8-V to 5.5-V supply voltage.

The LP87332A-Q1 has the following features:

  • DVS support with programmable slew rate
  • Automatic mode control based on the loading (PFM or PWM mode)
  • Forced PWM mode option
  • Optional external clock input to minimize crosstalk
  • Optional spread-spectrum technique to reduce EMI
  • Phase control for optimized EMI
  • Synchronous rectification
  • Current mode loop with PI compensator
  • Soft start
  • Power Good flag with maskable interrupt
  • Power Good signal (PGOOD) with selectable sources
  • Average output current sensing (for PFM entry and load current measurement)

The following parameters can be programmed via registers, the default values are set by OTP bits:

  • Output voltage
  • Forced PWM operation
  • Switch current limit
  • Output voltage slew rate
  • Enable and disable delays

There are two modes of operation for the buck converter, depending on the output current required: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption when forced PWM mode is disabled. The forced PWM mode can be selected to maintain fixed switching frequency at all load current levels.

A block diagram of a single core is shown in Figure 6.

LP87332A-Q1 Detailed_Block.gif Figure 6. Detailed Block Diagram Showing One Core

Transition Between PWM and PFM Modes

PWM mode operation optimizes efficiency at mid to full load at the expense of light-load efficiency. The LP87332A-Q1 converter operates in PWM mode at load current of about 600 mA or higher. At lighter load current levels the device automatically switches into PFM mode for reduced current consumption when forced PWM mode is disabled (AUTO mode operation). By combining the PFM and the PWM modes a high efficiency is achieved over a wide output-load current range.

Buck Converter Load Current Measurement

Buck load current can be monitored via I2C registers. The monitored buck converter is selected with the LOAD_CURRENT_BUCK_SELECT bit in SEL_I_LOAD register. A write to this selection register starts a current measurement sequence. The regulator is automatically forced to PWM mode for the measurement period. The measurement sequence is 50 µs long, maximum.

LP87332A-Q1 can be configured to give out an interrupt (I_MEAS_INT bit in INT_TOP_1 register) after the load current measurement sequence is finished. Load current measurement interrupt can be masked with I_MEAS_MASK bit (TOP_MASK_1 register). The measurement result can be read from registers I_LOAD_1 and I_LOAD_2. Register I_LOAD_1 bits BUCK_LOAD_CURRENT[7:0] give out the LSB bits and register I_LOAD_2 bit BUCK_LOAD_CURRENT[8] the MSB bit. The measurement result BUCK_LOAD_CURRENT[8:0] LSB is 20 mA, and maximum code value of the measurement corresponds to 10.22 A.

Spread-Spectrum Mode

Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add EMI-filters and shields to the boards. The LP87332A-Q1 has register selectable spread-spectrum mode which minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency varies around the center frequency, reducing the EMI emissions radiated by the converter and associated passive components and PCB traces (see Figure 7). This feature is available only when internal RC oscillator is used (EN_PLL bit is 0 in PLL_CTRL register), and it is enabled with the EN_SPREAD_SPEC bit in CONFIG register, and it affects both buck cores.

LP87332A-Q1 30190611.gif
Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread spectrum architecture of the LP87332A-Q1 spreads that energy over a large bandwidth.
Figure 7. Spread-Spectrum Modulation

Sync Clock Functionality

The LP87332A-Q1 device contains a CLKIN input to synchronize the switching clock of the buck regulators with the external clock. The block diagram of the clocking and PLL module is shown in Figure 8. Depending on the EN_PLL bit in PLL_CTRL register and the external clock availability, the external clock is selected and interrupt is generated as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK_1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits in PLL_CTRL register, and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy limits (–30%/+10%) of the selected frequency for valid clock detection.

The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases where the external clock is expected but it is not available. These cases are start-up (read OTP-to-standby transition) when EN_PLL is 1 and Buck regulator enable (standby-to-active transition) when EN_PLL is 1.

LP87332A-Q1 Clock_PLL.gif Figure 8. Clock and PLL Module

Table 2. PLL Operation

DEVICE OPERATION MODEEN_PLLPLL AND CLOCK DETECTOR STATEINTERRUPT FOR EXTERNAL CLOCKCLOCK
STANDBY0DisabledNoInternal RC
ACTIVE0DisabledNoInternal RC
STANDBY1EnabledWhen external clock appears or disappearsAutomatic change to external clock when available
ACTIVE1EnabledWhen external clock appears or disappearsAutomatic change to external clock when available

Low-Dropout Linear Regulators (LDOs)

The LP87332A-Q1 device includes two identical linear regulators, LDO0 and LDO1, targeting analog loads with low noise requirements. The LDO regulators deliver 0.8-V to 3.3-V regulated voltage rails from a 2.5-V to 5.5-V input voltage. Both regulators have dedicated inputs which can be higher or lower than the device system voltage V(VANA) to minimize the power dissipation.

Power-Up

The power-up sequence for the LP87332A-Q1 is as follows:

  • VANA (and VIN_Bx) reach minimum recommended levels (VVANA > VANAUVLO). This initiates power-on-reset (POR), OTP reading, and enables the system I/O interface. The I2C host should allow at least 1.2 ms before writing or reading data to the LP87332A-Q1.
  • Device enters standby mode.
  • The host can change the default register setting by I2C if needed.
  • The regulators can be enabled/disabled and the GPO signals can be controlled by EN pin and by I2C interface.

Transitions between the operating modes are shown in Modes of Operation.

Regulator Control

Enabling and Disabling Regulators

The regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways for enable and disable the buck regulators:

  • Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 0 in BUCKx_CTRL_1 register)
  • Using EN control pin (BUCKx_EN bit is 1 AND BUCKx_EN_PIN_CTRL bit is 1)

Similarly there are two ways to enable and disable the LDO regulators:

  • Using LDOx_EN bit in LDOx_CTRL register (LDOx_EN_PIN_CTRL bit is 0 in LDOx_CTRL register)
  • Using EN control pin (LDOx_EN bit is 1 AND LDOx_EN_PIN_CTRL bit is 1)

If the EN control pin is used for enable and disable then the delay from the control signal rising edge to start-up is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and LDOx_STARTUP_DELAY[3:0] bits in LDOx_DELAY register and the delay from control signal falling edge to shutdown is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register and LDOx_SHUTDOWN_DELAY[3:0] bits in LDOx_DELAY register. The delays are valid only for EN signal transitions and not for control with I2C writings to BUCKx_EN and LDOx_EN bits.

The control of the regulator (with 0-ms delays) is shown in Table 3.

Table 3. Regulator Control

BUCKx_EN /
LDOx_EN
BUCKx_EN_PIN_CTRL /
LDOx_EN_PIN_CTRL
EN PINBUCKx OUTPUT VOLTAGE /
LDOx OUTPUT VOLTAGE
Enable/disable control with BUCKx_EN/LDOx_EN bit0Don't CareDon't CareDisabled
10Don't CareBUCKx_VSET[7:0] / LDOx_VSET[4:0]
Enable/disable control with EN pin11LowDisabled
11HighBUCKx_VSET[7:0] / LDOx_VSET[4:0]

The buck regulator is enabled by the EN pin or by I2C writing as shown in Figure 9. The soft-start circuit limits the in-rush current during start-up. When the output voltage rises to a 0.35-V level, the output voltage becomes slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase above the 0.35-V level in 1 ms or the output voltage drops below 0.35-V level during operation (for minimum of 1 ms), the regulator is disabled, and BUCKx_SC_INT interrupt in INT_BUCK register is set. When the output voltage reaches the Power-Good threshold level the BUCKx_PG_INT interrupt flag in INT_BUCK register is set. The Power-Good interrupt flag when reaching valid output voltage can be masked using BUCKx_PGR_MASK bit in BUCK_MASK register. The Power-Good interrupt flag can be also generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection is set by BUCKx_PGF_MASK bit in BUCK_MASK register. A BUCKx_PG_STAT bit in BUCK_STAT register shows always the validity of the output voltage: 1 means valid and 0 means invalid output voltage. A PGOOD_WINDOW_BUCK bit in PGOOD_CTRL_1 register sets the detection method for the valid buck output voltage, either undervoltage detection or undervoltage and overvoltage detection.

LP87332A-Q1 Enable_Disable_Buck.gif Figure 9. Buck Regulator Enable and Disable

The LDO regulator is enabled by the EN pin or by I2C writing as shown in Figure 10. The soft-start circuit limits the in-rush current during start-up. Output voltage increase rate is less than 100 mV/μsec during soft-start. If there is a short circuit at the output, and the output voltage does not increase above the 0.3-V level in 1 ms or the output voltage drops below 0.3-V level during operation (for minimum of 1 ms), the regulator is disabled, and LDOx_SC_INT interrupt in INT_LDO register is set. When the output voltage reaches the Power-Good threshold level the LDOx_PG_INT interrupt flag in INT_LDO register is set. The Power-Good interrupt flag when reaching valid output voltage can be masked using LDOx_PGR_MASK bit in LDO_MASK register. The Power-Good interrupt flag can be also generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection is set by LDOx_PGF_MASK bit in LDO_MASK register. A LDOx_PG_STAT bit in LDO_STAT register shows always the validity of the output voltage; 1 means valid, and 0 means invalid output voltage. A PGOOD_WINDOW_LDO bit in PGOOD_CTRL_1 register sets the detection method for the valid LDO output voltage, either undervoltage detection or undervoltage and overvoltage detection.

LP87332A-Q1 Enable_Disable_LDO.gif Figure 10. LDO Regulator Enable and Disable

The EN input pin have an integrated pulldown resistor. The pulldown resistor is controlled with EN_PD bit in CONFIG register.

Changing Output Voltage

The output voltage of the regulator can be changed by writing to the BUCKx_VOUT / LDOx_VOUT register. The voltage change for buck regulator is always slew-rate controlled, and the slew-rate is defined by the BUCKx_SLEW_RATE[2:0] bits in BUCKx_CTRL_2 register. During voltage change the forced PWM mode is used automatically. When the programmed output voltage is achieved, the mode becomes the one defined by load current, and the BUCKx_FPWM bit in BUCKx_CTRL_1 register.

The voltage change and Power-Good interrupts are shown in Figure 11.

LP87332A-Q1 Voltage_Change.gif Figure 11. Regulator Output Voltage Change

During an LDO voltage change the internal reference for the Power-Good detection is also changed. For this reason the Power Good may toggle during the LDO voltage change can indicate valid output even when the output voltage is changing. This period takes less than 100 µs and after that time the Power Good gives correct value.

Enable and Disable Sequences

The LP87332A-Q1 device supports start-up and shutdown sequencing with programmable delays for different regulator outputs using single EN control signal. The Buck regulator is selected for delayed control with:

  • BUCKx_EN = 1 in BUCKx_CTRL_1 register
  • BUCKx_EN_PIN_CTRL = 1 in BUCKx_CTRL_1 register
  • BUCKx_VSET[7:0] bits in BUCKx_VOUT register defines the voltage when EN pin is high
  • The delay from rising edge of EN pin to the regulator enable is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and
  • The delay from falling edge of EN pin to the regulator disable is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register.

In the same way the LDO regulator is selected for delayed control with:

  • LDOx_EN = 1 in LDOx_CTRL register
  • LDOx_EN_PIN_CTRL = 1 in LDOx_CTRL register
  • LDOx_VSET[4:0] bits in LDOx_VOUT register defines the voltage when EN pin is high
  • The delay from rising edge of EN pin to the regulator enable is set by LDOx_STARTUP_DELAY[3:0] bits in LDOx_DELAY register and
  • The delay from falling edge of EN pin to the regulator disable is set by LDOx_SHUTDOWN_DELAY[3:0] bits in LDOx_DELAY register.

The GPO (and GPO2) digital output signals can be also controlled as a part of start-up and shutdown sequencing with the following settings:

  • GPOx_EN = 1 in GPO_CTRL register
  • GPOx_EN_PIN_CTRL = 1 in GPO_CTRL register
  • The delay from rising edge of EN pin to the rising edge of GPO/GPO2 signal is set by GPOx_STARTUP_DELAY[3:0] bits in GPOx_DELAY register and
  • The delay from falling edge of EN pin to the falling edge of GPO/GPO2 signal is set by GPOx_SHUTDOWN_DELAY[3:0] bits in GPOx_DELAY register.

An example of the start-up and shutdown sequences for the buck regulators are shown in Figure 12. The start-up and shutdown delays for the Buck0 regulator are 1 ms and 4 ms; for the Buck1 regulator start-up and shutdown delays are 3 ms and 1 ms. The delay settings are used only for enable/disable control with EN signal.

LP87332A-Q1 Sequencing.gif Figure 12. Start-Up and Shutdown Sequencing

Device Reset Scenarios

There are three reset methods implemented on the LP87332A-Q1:

  • Software reset with SW_RESET bit in RESET register
  • Undervoltage lockout (UVLO) reset from VANA supply

An SW reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event disables all the regulators immediately, drives GPO and GPO2 signals low, resets all the register bits to the default values and OTP bits are loaded (see Figure 18). I2C interface is not reset during software reset.

If VANA supply voltage falls below the UVLO threshold level then all the regulators are disabled immediately, GPO and GPO2 signals are driven low, and all the register bits are reset to the default values. When the VANA supply voltage transition above UVLO threshold level an internal POR occurs. OTP bits are loaded to the registers and a startup is initiated according to the register settings.

Diagnosis and Protection Features

The LP87332A-Q1 is capable of providing four levels of protection features:

  • Information of valid regulator output voltage which sets interrupt or PGOOD signal;
  • Warnings for diagnosis which sets interrupt;
  • Protection events which are disabling the regulators; and
  • Faults which are causing the device to shutdown.

The LP87332A-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared.

When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, the interrupt is not generated. The mask bit change with I2C does not affect, because the RESET_REG_MASK bit is loaded from OTP during reset sequence.

Table 4. Summary of Interrupt Signals

EVENTOUTCOMEINTERRUPT BITINTERRUPT MASK BITSTATUS BITRECOVERY/INTERRUPT CLEAR
Buck current limit triggeredNo effectBUCK_INT
BUCKx_ILIM_INT
BUCKx_ILIM_MASKBUCKx_ILIM_STATWrite 1 to BUCKx_ILIM_INT bit
Interrupt is not cleared if current limit is active
LDO current limit triggeredNo effectLDO_INT
LDOx_ILIM_INT
LDOx_ILIM_MASKLDOx_ILIM_STATWrite 1 to LDOx_ILIM_INT bit
Interrupt is not cleared if current limit is active
Buck short circuit (VVOUT < 0.35 V at 1 ms after enable) or overload (VVOUT decreasing below 0.35 V during operation, 1-ms debounce)Regulator disableBUCK_INT
BUCKx_SC_INT
N/AN/AWrite 1 to BUCKx_SC_INT bit
LDO short circuit (VVOUT < 0.3 V at 1 ms after enable) or overload (VVOUT decreasing below 0.3 V during operation, 1-ms debounce)Regulator disableLDO_INT
LDOx_SC_INT
N/AN/AWrite 1 to LDOx_SC_INT bit
Thermal sarningNo effectTDIE_WARN_INTTDIE_WARN_MASKTDIE_WARN_STATWrite 1 to TDIE_WARN_INT bit
Interrupt is not cleared if temperature is above thermal warning level
Thermal shutdownAll regulators disabled immediately and GPO and GPO2 are set to lowTDIE_SD_INTN/ATDIE_SD_STATWrite 1 to TDIE_SD_INT bit
Interrupt is not cleared if temperature is above thermal shutdown level
VANA overvoltage (VANAOVP)All regulators disabled immediately and GPO and GPO2 are set to lowOVP_INTN/AOVP_STATWrite 1 to OVP_INT bit
Interrupt is not cleared if VANA voltage is above VANAOVP level
Buck power good, output voltage becomes validNo effectBUCK_INT
BUCKx_PG_INT
BUCKx_PGR_MASKBUCKx_PG_STATWrite 1 to BUCKx_PG_INT bit
Buck power good, output voltage becomes invalidNo effectBUCK_INT
BUCKx_PG_INT
BUCKx_PGF_MASKBUCKx_PG_STATWrite 1 to BUCKx_PG_INT bit
LDO Power Good, output voltage becomes validNo effectLDO_INT
LDOx_PG_INT
LDOx_PGR_MASKLDOx_PG_STATWrite 1 to LDOx_PG_INT bit
LDO power good, output voltage becomes invalidNo effectLDO_INT
LDOx_PG_INT
LDOx_PGF_MASKLDOx_PG_STATWrite 1 to LDOx_PG_INT bit
PGOOD pin changing from active to inactive state(1)No effectPGOOD_INTPGOOD_MASKPGOOD_STATWrite 1 to PGOOD_INT bit
External clock appears or disappearsNo effect to regulatorsSYNC_CLK_INT(2)SYNC_CLK_MASKSYNC_CLK_STATWrite 1 to SYNC_CLK_INT bit
Load current measurement ready No effectI_MEAS_INTI_MEAS_MASKN/AWrite 1 to I_MEAS_INT bit
Supply voltage VANAUVLO triggered (VANA falling)Immediate shutdown, registers reset to default valuesN/AN/AN/AN/A
Supply voltage VANAUVLO triggered (VANA rising)Startup, registers reset to default values and OTP bits loadedRESET_REG_INTRESET_REG_MASKN/AWrite 1 to RESET_REG_INT bit
Software requested resetImmediate shutdown followed by power up, registers reset to default valuesRESET_REG_INTRESET_REG_MASKN/AWrite 1 to RESET_REG_INT bit
PGOOD_STAT bit is 1 when the PGOOD pin shows valid voltages. PGOOD_POL bit in PGOOD_CTRL_1 register affects only PGOOD pin polarity, not Power Good and PGOOD_INT interrupt polarity.
Interrupt is generated during clock-detector operation and if clock is not available when clock detector is enabled.

Power-Good Information (PGOOD pin)

In addition to the interrupt-based indication of the current limit and the Power-Good level the LP87332A-Q1 device supports monitoring with PGOOD signal:

  • Regulator output voltage,
  • Input supply overvoltage,
  • Thermal warning and
  • Thermal shutdown.

Regulator output voltage monitoring (not current limit monitoring) can be selected for PGOOD indication. This selection is individual for both buck regulators and both LDO regulators and is set by EN_PGOOD_BUCKx bits in PGOOD_CTRL_1 register and EN_PGOOD_LDOx bits in PGOOD_CTRL_1 register. When a regulator is disabled, the monitoring is automatically masked to prevent it forcing PGOOD inactive. A thermal warning can be also selected for PGOOD indication with EN_PGOOD_TWARN bit in PGOOD_CTRL_2 register. The monitoring from all the output rails, thermal warning (TDIE_WARN_STAT), input overvoltage interrupt (OVP_INT), and thermal shutdown interrupt (TDIE_SD_INT) are combined, and PGOOD pin is active only if all the selected sources shows a valid status.

The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW_x bits in PGOOD_CTRL_1 register. If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and overvoltage are monitored.

The polarity and the output type (push-pull or open-drain) are selected by the PGOOD_POL and PGOOD_OD bits in the PGOOD_CTRL_1 register.

PGOOD is only active or asserted when all enabled power resource output voltages are within specified tolerance for each requested/programmed output voltage.

PGOOD is inactive or de-asserted if any enabled power resource output voltages is outside specified tolerance for each requested/programmed output voltage.

The device OTP setting selects either gated (that is, unusual) or continuous (that is, invalid) mode of operation.

PGOOD Pin Gated mode

The gated (or unusual) mode of operation is selected by setting PGOOD_MODE bit to 0 in PGOOD_CTRL_2 register.

For the gated mode of operation, PGOOD behaves as follows:

  • PGOOD is set to active or asserted state upon exiting OTP configuration as an initial default state.
  • PGOOD status is suspended or unchanged during an 800-µs gated time period, thereby gating-off the status indication.
  • During normal power-up sequencing and requested voltage changes, PGOOD state is not changed during an 800-µs gated time period. It typically remains active or asserted for normal conditions.
  • During an abnormal power-up sequencing and requested voltage changes, PGOOD status could change to inactive or de-asserted after an 800-µs gated time period if any output voltage is outside of regulation range.
  • Using the gated mode of operation could allow the PGOOD signal to initiate an immediate power shutdown sequence if the PGOOD signal is wired-OR with signal connected to EN input. This type of circuit configuration provides a smart PORz function for processor that eliminates the need for additional components to generate PORz upon start-up and to monitor voltage levels of key voltage domains.

The fault sets corresponding fault bit 1 in PG_FAULT register. The detected fault must be cleared to continue the PGOOD monitoring. The overvoltage and thermal shutdown are cleared by writing 1 to the OVP_INT and TDIE_SD_INT interrupt bits in INT_TOP_1 register. The regulator fault is cleared by writing 1 to the corresponding register bit in PG_FAULT register. The interrupts can be also cleared with VANA UVLO by toggling the input supply. An example of PGOOD pin operation in gated mode is shown in Figure 13.

LP87332A-Q1 PGOOD_Mode0_v2.gif Figure 13. PGOOD Pin Operation in Gated Mode

PGOOD Pin Continuous Mode

The continuous (or unvalid) mode of operation is selected by setting PGOOD_MODE bit to 1 in PGOOD_CTRL_2 register.

For the continuous mode of operation, PGOOD behaves as follows:

  • PGOOD is set to active or asserted state upon exiting OTP configuration.
  • PGOOD is set to inactive or de-asserted as soon as regulator is enabled.
  • PGOOD status begins indicating output voltage regulation status immediately and continuously.
  • During power-up sequencing and requested voltage changes, PGOOD will toggle between inactive or de-asserted while output voltages are outside of regulation ranges and active or asserted when inside of regulation ranges.

The PG_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing 1 to the bit. The PGOOD signal indicates also a thermal shutdown and input overvoltage interrupts, which are cleared by clearing the interrupt bits.

When regulator voltage is transitioning from one target voltage to another, the PGOOD signal is set inactive.

When the PGOOD signal becomes inactive, the source for the fault can be read from PG_FAULT register. If the invalid output voltage becomes valid again the PGOOD signal becomes active. Thus the PGOOD signal shows all the time if the monitored output voltages are valid. The block diagram for this operation is shown in Figure 14 and an example of operation is shown in Figure 15.

The PGOOD signal can be also configured so that it maintains inactive state even when the monitored outputs are valid but there are PG_FAULT_x bits in PG_FAULT register pending clearance. This type of operation is selected by setting PGFAULT_GATES_PGOOD bit to 1 in PGOOD_CTRL_2 register.

LP87332A-Q1 PGOOD_Block.gif Figure 14. PGOOD Block Diagram (Continuous Mode)
LP87332A-Q1 PGOOD_Mode1_v2.gif Figure 15. PGOOD Pin Operation in Continuous Mode

Warnings for Diagnosis (Interrupt)

Output Power Limit

The Buck regulators have programmable output peak current limits. The limits are individually programmed for both regulators with BUCKx_ILIM[2:0] bits in BUCKx_CTRL_2 register. If the load current is increased so that the current limit is triggered, the regulator continues to regulate to the limit current level (peak current regulation). The voltage may decrease if the load current is higher than limit current. If the current regulation continues for 20 µs, the LP87332A-Q1 device sets the BUCKx_ILIM_INT bit in INT_BUCK register and pulls the nINT pin low. The host processor can read BUCKx_ILIM_STAT bits in BUCK_STAT register to see if the regulator is still in peak current regulation mode and the interrupt is cleared by writing 1 to BUCKx_ILIM_INT bit. The current limit interrupt can be masked by setting BUCKx_ILIM_MASK bit in BUCK_MASK register to 1. The Buck overload situation is shown in Figure 16.

LP87332A-Q1 Overload_Buck.gif Figure 16. Buck Regulator Overload Situation

The LDO regulators include also current limit circuitry. If the load current is increased so that the current limit is triggered, the regulator limits the output current to the threshold level. The voltage may decrease if the load current is higher than the current limit. If the current regulation continues for 20 µs, the LP87332A-Q1 device sets the LDOx_ILIM_INT bit in INT_LDO register and pulls the nINT pin low. The host processor can read LDOx_ILIM_STAT bits in LDO_STAT register to see if the regulator is still in current regulation mode and the interrupt is cleared by writing 1 to LDOx_ILIM_INT bit. The current limit interrupt can be masked by setting LDOx_ILIM_MASK bit in LDO_MASK register to 1. The LDO overload situation is shown in Figure 17.

LP87332A-Q1 Overload_LDO.gif Figure 17. LDO Regulator Overload Situation

Thermal Warning

The LP87332A-Q1 device includes a protection feature against overtemperature by setting an interrupt for host processor. The threshold level of the thermal warning is selected with TDIE_WARN_LEVEL bit in CONFIG register.

If the LP87332A-Q1 device temperature increases above thermal warning level the device sets TDIE_WARN_INT bit in INT_TOP_1 register and pulls the nINT pin low. The status of the thermal warning can be read from TDIE_WARN_STAT bit in TOP_STAT register, and the interrupt is cleared by writing 1 to TDIE_WARN_INT bit. The thermal warning interrupt can be masked by setting TDIE_WARN_MASK bit in TOP_MASK_1 register to 1.

Protection (Regulator Disable)

If the regulator is disabled because of protection or fault (short-circuit protection, overload protection, thermal shutdown, input overvoltage protection, or UVLO), the output power FETs are set to high-impedance mode, and the output pulldown resistor is enabled (if enabled with BUCKx_RDIS_EN bit in BUCKx_CTRL_1 register and LDOx_RDIS_EN bit in LDOx_CTRL register). The turnoff time of the output voltage is defined by the output capacitance, load current, and the resistance of the integrated pull-down resistor. The pulldown resistors are active as long as VANA voltage is above approximately a 1.2-V level.

Short-Circuit and Overload Protection

A short-circuit protection feature allows the LP87332A-Q1 to protect itself and external components against short circuit at the output or against overload during start-up. For buck and LDO regulators the fault thresholds are about 350 mV (buck) and 300 mV (LDO), and the protection is triggered and the regulator is disabled if the output voltage is below the threshold level 1 ms after the regulator is enabled.

In a similar way the overload situation is protected during normal operation. If the output voltage falls below 0.35 V and 0.3 V and remains below the threshold level for 1 ms the regulator is disabled.

In buck regulator short-circuit and overload situations the BUCKx_SC_INT bit in INT_BUCK register and the INT_BUCKx bit in INT_TOP_1 register are set to 1, the BUCKx_STAT bit in BUCK_STAT register is set to 0, and the nINT signal is pulled low. In LDO regulator short-circuit and overload situations the LDOx_SC_INT bit in INT_LDO register and the INT_LDOx bit in INT_TOP_1 register are set to 1, the LDOx_STAT bit in LDO_STAT register is set to 0, and the nINT signal is pulled low. The host processor clears the interrupt by writing 1 to the BUCKx_SC_INT or to the LDOx_SC_INT bit. Upon clearing the interrupt the regulator makes a new start-up attempt if the regulator is in an enabled state.

Overvoltage Protection

The LP87332A-Q1 device monitors the input voltage from the VANA pin in standby and active operation modes. If the input voltage rises above VANAOVP voltage level, all the regulators are disabled immediately (without switching ramp, no shutdown delays), pulldown resistors discharge the output voltages if they are enabled (BUCKx_RDIS_EN = 1 in BUCKx_CTRL_1 register and LDOx_RDIS_EN = 1 in LDOx_CTRL register), GPOs are set to logic low level, nINT signal is pulled low, OVP_INT bit in INT_TOP_1 register is set to 1, and BUCKx_STAT bit in BUCK_STAT register and LDOx_STAT bit in LDO_STAT register are set to 0. The host processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above overvoltage detection level the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit in TOP_STAT register. Regulators cannot be enabled as long as the input voltage is above overvoltage detection level or the overvoltage interrupt is pending.

Thermal Shutdown

The LP87332A-Q1 has an overtemperature protection function that operates to protect itself from short-term misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are disabled immediately (without switching ramp, no shutdown delays), the TDIE_SD_INT bit in INT_TOP_1 register is set to 1, the nINT signal is pulled low, and the device enters STANDBY. nINT is cleared by writing 1 to the TDIE_SD_INT bit. If the temperature is above thermal shutdown level the interrupt is not cleared. The host can read the status of the thermal shutdown from the TDIE_SD_STAT bit in TOP_STAT register. Regulators cannot be enabled as long as the junction temperature is above thermal shutdown level or the thermal shutdown interrupt is pending.

Fault (Power Down)

Undervoltage Lockout

When the input voltage falls below VANAUVLO at the VANA pin, the buck and LDO regulators are disabled immediately (without switching ramp, no shutdown delays), and the output capacitor is discharged using the pulldown resistor, and the LP87332A-Q1 device enters SHUTDOWN. When V(VANA) voltage is above VANAUVLO threshold level, the device powers up to STANDBY state.

If the reset interrupt is unmasked by default (OTP bit for RESET_REG_MASK is 0 in TOP_MASK_2 register) the RESET_REG_INT interrupt bit in INT_TOP_2 register indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the RESET_REG_INT interrupt bit after detecting an nINT low signal, it knows that the input supply voltage has been below VANAUVLO level (or the host has requested reset with SW_RESET bit in RESET register), and the registers are reset to default values.

Operation of the GPO Signals

The LP87332A-Q1 device supports up to 2 general purpose output signals, GPO and GPO2. The GPO2 signal is multiplexed with CLKIN signal. The selection between CLKIN and GPO2 pin function is set with CLKIN_PIN_SEL bit in CONFIG register.

The GPO pins are configured with the following bits:

  • GPOx_OD bit in GPO_CTRL register defines the type of the output, either push-pull with V(VANA) level or open drain

The logic level of the GPOx pin is set by EN_GPOx bit in GPO_CTRL register.

The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence with EN pin is selected by GPOx_EN_PIN_CTRL bit in GPO_CTRL register. For start-up and shutdown sequence control see Enable and Disable Sequences.

Digital Signal Filtering

The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter. This results as an accuracy of one clock period for the debounce window.

Table 5. Digital Signal Filtering

EVENTSIGNAL/SUPPLYRISING EDGEFALLING EDGE
LENGTHLENGTH
Enable/disable for BUCKx, LDOx or GPOxEN3 µs(1)3 µs(1)
VANA UVLOVANA3 µs(1) (VANA voltage rising)Immediate (VANA voltage falling)
VANA overvoltageVANA1 µs (VANA voltage rising)20 µs (VANA voltage falling)
Thermal warningTDIE_WARN_INT20 µs20 µs
Thermal shutdownTDIE_SD_INT20 µs20 µs
Current limitVOUTx_ILIM20 µs20 µs
OverloadFB_B0, FB_B1, VOUT_LDO0, VOUT_LDO11 msN/V
PGOOD pin and power-good interruptPGOOD / FB_B0, FB_B1, VOUT_LDO0, VOUT_LDO16 µs6 µs
No glitch filtering, only synchronization.

Device Functional Modes

Modes of Operation

    SHUTDOWN:The V(VANA) voltage is below VANAUVLO threshold level. All switch, reference, control, and bias circuitry of the LP87332A-Q1 device are turned off.
    READ OTP:The main supply voltage V(VANA) is above VANAUVLO level. The regulators are disabled, and the reference and bias circuitry of the LP87332A-Q1 are enabled. The OTP bits are loaded to registers.
    STANDBY:The main supply voltage V(VANA) is above VANAUVLO level. The regulators are disabled, and the reference, control and bias circuitry of the LP87332A-Q1 are enabled. All registers can be read or written by the host processor via the system serial interface. The regulators can be enabled if needed.
    ACTIVE:The main supply voltage V(VANA) is above VANAUVLO level. At least one regulator is enabled. All registers can be read or written by the host processor via the system serial interface.

The operating modes and transitions between the modes are shown in Figure 18.

LP87332A-Q1 Operation_Modes.gif Figure 18. Device Operation Modes

Programming

I2C-Compatible Interface

The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed on the line and remain HIGH even when the bus is idle. The LP87332A-Q1 supports standard mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).

Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when clock signal is LOW.

LP87332A-Q1 30190620.gif Figure 19. Data Validity Diagram

Start and Stop Conditions

The LP87332A-Q1 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C master always generates the START and STOP conditions.

LP87332A-Q1 30190621.gif Figure 20. Start and Stop Sequences

The I2C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I2C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 21 shows the SDA and SCL signal timing for the I2C-compatible bus. See the Figure 1 for timing values.

LP87332A-Q1 30190619.gif Figure 21. I2C-Compatible Timing

Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP87332A-Q1 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP87332A-Q1 generates an acknowledge after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

NOTE

If the V(VANA) voltage is below VANAUVLO threshold level during I2C communication the LP87332A-Q1 device does not drive SDA line. The ACK signal and data transfer to the master is disabled at that time.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1 indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register.

LP87332A-Q1 30190622.gif Figure 22. Write Cycle (w = write; SDA = 0). Example Device Address = 0x60
LP87332A-Q1 30190623.gif
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
Figure 23. Read Cycle (r = read; SDA = 1). Example Device Address = 0x60

I2C-Compatible Chip Address

NOTE

The device address for the LP87332A-Q1 is 0x60.

After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data is written. The third byte contains the data for the selected register.

LP87332A-Q1 Chip_Address.gif
Here in an example with device address of 1100000Bin = 60Hex.
Figure 24. Device Address Example

Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the LP87332A-Q1, the internal address index counter is incremented by one and the next register is written. Table 6 shows writing sequence to two consecutive registers. Note that auto increment feature does not work for read.

Table 6. Auto-Increment Example

MASTER ACTIONSTARTDEVICE ADDRESS = 0x60WRITEREGISTER ADDRESSDATADATASTOP
LP87332A-Q1ACKACKACKACK

Register Maps

Register Descriptions

The LP87332A-Q1 is controlled by a set of registers through the I2C-compatible interface. The device registers, their addresses and their abbreviations are listed in Table 7. A more detailed description is given in the DEV_REV to I_LOAD_1 sections.

The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state.

NOTE

This register map describes the default values for a device with orderable code of LP87332ARHDRQ1. For other device versions the default values read from OTP memory can be different.

Table 7. Summary of LP87332A-Q1 Control Registers

AddrRegisterRead / WriteD7D6D5D4D3D2D1D0
0x00DEV_REVRDEVICE_ID[1:0]Reserved
0x01OTP_REVROTP_ID[7:0]
0x02BUCK0_
CTRL_1
R/WReservedBUCK0_FPWMBUCK0_RDIS_ENBUCK0_
EN_PIN_CTRL
BUCK0_EN
0x03BUCK0_
CTRL_2
R/WReservedBUCK0_ILIM[2:0]BUCK0_SLEW_RATE[2:0]
0x04BUCK1_
CTRL_1
R/WReservedBUCK1_FPWMBUCK1_RDIS_ENBUCK1_
EN_PIN_CTRL
BUCK1_EN
0x05BUCK1_
CTRL_2
R/WReservedBUCK1_ILIM[2:0]BUCK1_SLEW_RATE[2:0]
0x06BUCK0_
VOUT
R/WBUCK0_VSET[7:0]
0x07BUCK1_
VOUT
R/WBUCK1_VSET[7:0]
0x08LDO0_
CTRL
R/WReservedLDO0_RDIS_ENLDO0_
EN_PIN_CTRL
LDO0_EN
0x09LDO1_
CTRL
R/WReservedLDO1_RDIS_ENLDO1_
EN_PIN_CTRL
LDO1_EN
0x0ALDO0_
VOUT
R/WReservedLDO0_VSET[4:0]
0x0BLDO1_
VOUT
R/WReservedLDO1_VSET[4:0]
0x0CBUCK0_
DELAY
R/WBUCK0_SHUTDOWN_DELAY[3:0]BUCK0_STARTUP_DELAY[3:0]
0x0DBUCK1_
DELAY
R/WBUCK1_SHUTDOWN_DELAY[3:0]BUCK1_STARTUP_DELAY[3:0]
0x0ELDO0_
DELAY
R/WLDO0_SHUTDOWN_DELAY[3:0]LDO0_STARTUP_DELAY[3:0]
0x0FLDO1_
DELAY
R/WLDO1_SHUTDOWN_DELAY[3:0]LDO1_STARTUP_DELAY[3:0]
0x10GPO_
DELAY
R/WGPO_SHUTDOWN_DELAY[3:0]GPO_STARTUP_DELAY[3:0]
0x11GPO2_
DELAY
R/WGPO2_SHUTDOWN_DELAY[3:0]GPO2_STARTUP_DELAY[3:0]
0x12GPO_
CTRL
R/WReservedGPO2_ODGPO2_
EN_PIN_CTRL
GPO2_ENReservedGPO_ODGPO_
EN_PIN_CTRL
GPO_EN
0x13CONFIGR/WReservedSTARTUP_DELAY_SELSHUTDOWN_DELAY_SELCLKIN_PIN_SELCLKIN_PDEN_PDTDIE
_WARN
_LEVEL
EN_
SPREAD
_SPEC
0x14PLL_CTRLR/WReservedEN_PLLReservedEXT_CLK_FREQ[4:0]
0x15PGOOD_CTRL_1R/WPGOOD_POLPGOOD_ODPGOOD_WINDOW_LDOPGOOD_WINDOW_BUCKEN_PGOOD_LDO1EN_PGOOD_LDO0EN_PGOOD_BUCK1EN_PGOOD_BUCK0
0x16PGOOD_CTRL_2R/WReservedEN_PGOOD_TWARNPG_FAULT_GATES_PGOODPGOOD_MODE
0x17PG_FAULTRReservedPG_FAULT_LDO1PG_FAULT_LDO0PG_FAULT_BUCK1PG_FAULT_BUCK0
0x18RESETR/WReservedSW_
RESET
0x19INT_TOP_1R/WPGOOD_
INT
INT_
LDO
INT_
BUCK
SYNC_
CLK_INT
TDIE_SD_INTTDIE_
WARN_INT
OVP_INTI_MEAS_
INT
0x1AINT_TOP_2R/WReservedRESET_
REG_INT
0x1BINT_BUCKR/WReservedBUCK1_
PG_INT
BUCK1_
SC_INT
BUCK1_
ILIM_INT
ReservedBUCK0_
PG_INT
BUCK0_
SC_INT
BUCK0_
ILIM_INT
0x1CINT_LDOR/WReservedLDO1_
PG_INT
LDO1_
SC_INT
LDO1_
ILIM_INT
ReservedLDO0_
PG_INT
LDO0_
SC_INT
LDO0_
ILIM_INT
0x1DTOP_
STAT
RPGOOD_STATReservedSYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_
WARN_
STAT
OVP_
STAT
Reserved
0x1EBUCK_STATRBUCK1_
STAT
BUCK1_
PG_STAT
ReservedBUCK1_
ILIM_STAT
BUCK0_
STAT
BUCK0_
PG_STAT
ReservedBUCK0_
ILIM_STAT
0x1FLDO_STATRLDO1_
STAT
LDO1_
PG_STAT
ReservedLDO1_
ILIM_STAT
LDO0_
STAT
LDO0_
PG_STAT
ReservedLDO0_
ILIM_STAT
0x20TOP_
MASK_1
R/WPGOOD_
INT_MASK
ReservedSYNC_CLK
_MASK
ReservedTDIE_WARN_MASKReservedI_MEAS_
MASK
0x21TOP_
MASK_2
R/WReservedRESET_
REG_MASK
0x22BUCK_MASKR/WBUCK1_PGF_MASKBUCK1_PGR_MASKReservedBUCK1_
ILIM_
MASK
BUCK0_PGF_MASKBUCK0_PGR_MASKReservedBUCK0_
ILIM_
MASK
0x23LDO_MASKR/WLDO1_PGF_MASKLDO1_PGR_MASKReservedLDO1_
ILIM_
MASK
LDO0_PGF_MASKLDO0_PGR_MASKReservedLDO0_
ILIM_
MASK
0x24SEL_I_
LOAD
R/WReservedLOAD_CURRENT_
BUCK_SELECT
0x25I_LOAD_2RReservedBUCK_LOAD_CURRENT[8]
0x26I_LOAD_1RBUCK_LOAD_CURRENT[7:0]

DEV_REV

Address: 0x00

D7D6D5D4D3D2D1D0
DEVICE_ID[1:0]Reserved
BitsFieldTypeDefaultDescription
7:6DEVICE_ID[1:0]R0x0*Device specific ID code.
5:0ReservedR00 0010

OTP_REV

Address: 0x01

D7D6D5D4D3D2D1D0
OTP_ID[7:0]
BitsFieldTypeDefaultDescription
7:0OTP_ID[7:0]R 0x2A*Identification Code of the OTP EPROM Version.

BUCK0_CTRL_1

Address: 0x02

D7D6D5D4D3D2D1D0
ReservedBUCK0_FPWMBUCK0_RDIS_ENBUCK0_EN_PIN_CTRLBUCK0_EN
BitsFieldTypeDefaultDescription
7:4ReservedR/W0000
3BUCK0_FPWMR/W 0 *Buck0 mode selection:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation.
2BUCK0_RDIS_ENR/W1Enable output discharge resistor (RDIS_Bx) when Buck0 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
1BUCK0_EN_PIN
_CTRL
R/W 1 *Enable control for Buck0:
0 - only BUCK0_EN bit controls Buck0
1 - BUCK0_EN bit AND EN pin control Buck0.
0BUCK0_ENR/W 1 *Enable Buck0 regulator:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled.

BUCK0_CTRL_2

Address: 0x03

D7D6D5D4D3D2D1D0
ReservedBUCK0_ILIM[2:0]BUCK0_SLEW_RATE[2:0]
BitsFieldTypeDefaultDescription
7:6ReservedR/W00
5:3BUCK0_ILIM[2:0]R/W0x5*Sets the switch current limit of Buck0. Can be programmed at any time during operation:
0x0 - 1.5 A
0x1 - 2.0 A
0x2 - 2.5 A
0x3 - 3.0 A
0x4 - 3.5 A
0x5 - 4.0 A
0x6 - Reserved
0x7 - Reserved
2:0BUCK0_SLEW_RATE[2:0]R/W0x2*Sets the output voltage slew rate for Buck0 regulator (rising and falling edges):
0x0 - Reserved
0x1 - Reserved
0x2 - 10 mV/µs
0x3 - 7.5 mV/µs
0x4 - 3.8 mV/µs
0x5 - 1.9 mV/µs
0x6 - 0.94 mV/µs
0x7 - 0.47 mV/µs

BUCK1_CTRL_1

Address: 0x04

D7D6D5D4D3D2D1D0
ReservedBUCK1_FPWMBUCK1_RDIS_ENBUCK1_EN_PIN_CTRLBUCK1_EN
BitsFieldTypeDefaultDescription
7:4ReservedR/W0000
3BUCK1_FPWMR/W 0 *Buck1 mode selection:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation.
2BUCK1_RDIS_ENR/W1Enable output discharge resistor (RDIS_Bx) when Buck1 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
1BUCK1_EN_PIN
_CTRL
R/W 1 *Enable control for Buck1:
0 - only BUCK1_EN bit controls Buck1
1 - BUCK1_EN bit AND EN pin control Buck1.
0BUCK1_ENR/W 1 *Enable Buck1 regulator:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled.

BUCK1_CTRL_2

Address: 0x05

D7D6D5D4D3D2D1D0
ReservedBUCK1_ILIM[2:0]BUCK1_SLEW_RATE[2:0]
BitsFieldTypeDefaultDescription
7:6ReservedR/W00
5:3BUCK1_ILIM[2:0]R/W0x5*Sets the switch current limit of Buck1. Can be programmed at any time during operation:
0x0 - 1.5 A
0x1 - 2.0 A
0x2 - 2.5 A
0x3 - 3.0 A
0x4 - 3.5 A
0x5 - 4.0 A
0x6 - Reserved
0x7 - Reserved
2:0BUCK1_SLEW_RATE[2:0]R/W0x2*Sets the output voltage slew rate for Buck1 regulator (rising and falling edges):
0x0 - Reserved
0x1 - Reserved
0x2 - 10 mV/µs
0x3 - 7.5 mV/µs
0x4 - 3.8 mV/µs
0x5 - 1.9 mV/µs
0x6 - 0.94 mV/µs
0x7 - 0.47 mV/µs

BUCK0_VOUT

Address: 0x06

D7D6D5D4D3D2D1D0
BUCK0_VSET[7:0]
BitsFieldTypeDefaultDescription
7:0BUCK0_VSET[7:0]R/W0x59*Sets the output voltage of Buck0 regulator
Reserved, DO NOT USE
0x00 ... 0x13
0.7 V - 0.73 V, 10 mV steps
0x14 - 0.7V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V

BUCK1_VOUT

Address: 0x07

D7D6D5D4D3D2D1D0
BUCK1_VSET[7:0]
BitsFieldTypeDefaultDescription
7:0BUCK1_VSET[7:0]R/W0x59*Sets the output voltage of Buck0 regulator
Reserved, DO NOT USE
0x00 ... 0x13
0.7 V - 0.73 V, 10 mV steps
0x14 - 0.7V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V

LDO0_CTRL

Address: 0x08

D7D6D5D4D3D2D1D0
ReservedLDO0_RDIS_ENLDO0_EN_PIN_CTRLLDO0_EN
BitsFieldTypeDefaultDescription
7:3ReservedR/W0 0000
2LDO0_RDIS_ENR/W1Enable output discharge resistor (RDIS_LDOx) when LDO0 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
1LDO0_EN_PIN
_CTRL
R/W 1 *Enable control for LDO0:
0 - only LDO0_EN bit controls LDO0
1 - LDO0_EN bit AND EN pin control LDO0.
0LDO0_ENR/W 1 *Enable LDO0 regulator:
0 - LDO0 regulator is disabled
1 - LDO0 regulator is enabled.

LDO1_CTRL

Address: 0x09

D7D6D5D4D3D2D1D0
ReservedLDO1_RDIS_ENLDO1_EN_PIN_CTRLLDO1_EN
BitsFieldTypeDefaultDescription
7:3ReservedR/W0 0000
2LDO1_RDIS_ENR/W1Enable output discharge resistor (RDIS_LDOx) when LDO1 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
1LDO1_EN_PIN
_CTRL
R/W 0 *Enable control for LDO1:
0 - only LDO1_EN bit controls LDO1
1 - LDO1_EN bit AND EN pin control LDO1.
0LDO1_ENR/W 0 *Enable LDO1 regulator:
0 - LDO1 regulator is disabled
1 - LDO1 regulator is enabled.

LDO0_VOUT

Address: 0x0A

D7D6D5D4D3D2D1D0
ReservedLDO0_VSET[4:0]
BitsFieldTypeDefaultDescription
7:5ReservedR/W000
4:0LDO0_VSET[4:0]R/W0x0A*Sets the output voltage of LDO0 regulator
0.8 V - 3.3 V, 100 mV steps
0x00 - 0.8V
...
0x19 - 3.3 V
Reserved, DO NOT USE
0x1A ... 0x1F

LDO1_VOUT

Address: 0x0B

D7D6D5D4D3D2D1D0
ReservedLDO1_VSET[4:0]
BitsFieldTypeDefaultDescription
7:5ReservedR/W000
4:0LDO1_VSET[4:0]R/W0x11*Sets the output voltage of LDO1 regulator
0.8 V - 3.3 V, 100 mV steps
0x00 - 0.8V
...
0x19 - 3.3 V
Reserved, DO NOT USE
0x1A ... 0x1F

BUCK0_DELAY

Address: 0x0C

D7D6D5D4D3D2D1D0
BUCK0_SHUTDOWN_DELAY[3:0]BUCK0_STARTUP_DELAY[3:0]
BitsFieldTypeDefaultDescription
7:4BUCK0_
SHUTDOWN_
DELAY[3:0]
R/W0x1*Shutdown delay of Buck0 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0BUCK0_
STARTUP_
DELAY[3:0]
R/W0x4* Startup delay of Buck0 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

BUCK1_DELAY

Address: 0x0D

D7D6D5D4D3D2D1D0
BUCK1_SHUTDOWN_DELAY[3:0]BUCK1_STARTUP_DELAY[3:0]
BitsFieldTypeDefaultDescription
7:4BUCK1_
SHUTDOWN_
DELAY[3:0]
R/W0x1*Shutdown delay of Buck1 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0BUCK1_
STARTUP_
DELAY[3:0]
R/W0x3* Startup delay of Buck1 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

LDO0_DELAY

Address: 0x0E

D7D6D5D4D3D2D1D0
LDO0_SHUTDOWN_DELAY[3:0]LDO0_STARTUP_DELAY[3:0]
BitsFieldTypeDefaultDescription
7:4LDO0_
SHUTDOWN_
DELAY[3:0]
R/W0x2*Shutdown delay of LDO0 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0LDO0_
STARTUP_
DELAY[3:0]
R/W0x1* Startup delay of LDO0 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

LDO1_DELAY

Address: 0x0F

D7D6D5D4D3D2D1D0
LDO1_SHUTDOWN_DELAY[3:0]LDO1_STARTUP_DELAY[3:0]
BitsFieldTypeDefaultDescription
7:4LDO1_
SHUTDOWN_
DELAY[3:0]
R/W0x0*Shutdown delay of LDO1 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0LDO1_
STARTUP_
DELAY[3:0]
R/W0x0* Startup delay of LDO1 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

GPO_DELAY

Address: 0x10

D7D6D5D4D3D2D1D0
GPO_SHUTDOWN_DELAY[3:0]GPO_STARTUP_DELAY[3:0]
BitsFieldTypeDefaultDescription
7:4GPO_
SHUTDOWN_
DELAY[3:0]
R/W0x0*Delay for GPO falling edge from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0GPO_
STARTUP_
DELAY[3:0]
R/W0x5* Delay for GPO rising edge from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

GPO2_DELAY

Address: 0x11

D7D6D5D4D3D2D1D0
GPO2_SHUTDOWN_DELAY[3:0]GPO2_STARTUP_DELAY[3:0]
BitsFieldTypeDefaultDescription
7:4GPO2_
SHUTDOWN_
DELAY[3:0]
R/W0x0*Delay for GPO2 falling edge from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0GPO2_
STARTUP_
DELAY[3:0]
R/W0xA* Delay for GPO2 rising edge from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

GPO_CTRL

Address: 0x12

D7D6D5D4D3D2D1D0
ReservedGPO2_ODGPO2_EN_PIN_CTRLGPO2_ENReservedGPO_ODGPO_EN_PIN_CTRLGPO_EN
BitsFieldTypeDefaultDescription
7ReservedR0
6GP02_ODR/W 1 *GPO2 signal type when configured as General Purpose Output (CLKIN pin):
0 - Push-pull output (VANA level)
1 - Open-drain output
5GPO2_EN_PIN_CTRLR/W 1 *Control for GPO2:
0 - Only GPO2_EN bit controls GPO2
1 - GPO2_EN bit AND EN pin control GPO2.
4GPO2_ENR/W 1 *Output level of GPO2 signal (when configured as General Purpose Output):
0 - Logic low level
1 - Logic high level
3ReservedR0
2GPO_ODR/W 1 *GPO signal type:
0 - Push-pull output (VANA level)
1 - Open-drain output
1GPO_EN_PIN_CTRLR/W 1 *Control for GPO:
0 - Only GPO_EN bit controls GPO
1 - GPO_EN bit AND EN pin control GPO.
0GPO_ENR/W 1 *Output level of GPO signal:
0 - Logic low level
1 - Logic high level

CONFIG

Address: 0x13

D7D6D5D4D3D2D1D0
ReservedSTARTUP_DELAY_SELSHUTDOWN_DELAY_SELCLKIN_PIN_SELCLKIN_PDEN2_PDTDIE_WARN_
LEVEL
EN_SPREAD
_SPEC
BitsFieldTypeDefaultDescription
7ReservedR/W0
6STARTUP_DELAY_SELR/W 0 *Startup delay range from EN signals.
0 - 0 ms - 7.5 ms with 0.5 ms steps
1 - 0 ms - 15 ms with 1 ms steps
5SHUTDOWN_DELAY_SELR/W 0 *Shutdown delay range from EN signals.
0 - 0 ms - 7.5 ms with 0.5 ms steps
1 - 0 ms - 15 ms with 1 ms steps
4CLKIN_PIN_SELR/W 0 *CLKIN pin function:
0 - GPO2
1 - CLKIN
3CLKIN_PDR/W 0 *Selects the pull down resistor on the CLKIN input pin. (valid also when selected as GPO2)
0 - Pull-down resistor is disabled.
1 - Pull-down resistor is enabled.
2EN_PDR/W 1 *Selects the pull down resistor on the EN input pin.
0 - Pull-down resistor is disabled.
1 - Pull-down resistor is enabled.
1TDIE_WARN_
LEVEL
R/W 1 *Thermal warning threshold level.
0 - 125°C
1 - 137°C.
0EN_SPREAD
_SPEC
R/W 0 *Enable spread spectrum feature:
0 - Disabled
1 - Enabled

PLL_CTRL

Address: 0x14

D7D6D5D4D3D2D1D0
ReservedEN_PLLReservedEXT_CLK_FREQ[4:0]
BitsFieldTypeDefaultDescription
7ReservedR/W0
6EN_PLLR/W 0 *Selection of external clock and PLL operation:
0 - Forced to internal RC oscillator. PLL disabled.
1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use when available, interrupt generated if external clock appears or disappears.
5ReservedR/W0This bit must be set to '0'.
4:0EXT_CLK_FREQ[4:0]R/W0x01*Frequency of the external clock (CLKIN):
0x00 - 1 MHz
0x01 - 2 MHz
0x02 - 3 MHz
...
0x16 - 23 MHz
0x17 - 24 MHz
0x18...0x1F - Reserved
See electrical specification for input clock frequency tolerance.

PGOOD_CTRL_1

Address: 0x15

D7D6D5D4D3D2D1D0
PGOOD_POLPGOOD_ODPGOOD_
WINDOW_LDO
PGOOD_
WINDOW_BUCK
EN_PGOOD_LDO1EN_PGOOD_LDO0EN_PGOOD_BUCK1EN_PGOOD_BUCK0
BitsFieldTypeDefaultDescription
7PGOOD_POLR/W 0 *PGOOD signal polarity.
0 - PGOOD signal high when monitored outputs are valid
1 - PGOOD signal low when monitored outputs are valid
6PGOOD_ODR/W 1 *PGOOD signal type:
0 - Push-pull output (VANA level)
1 - Open-drain output
5PGOOD_
WINDOW_LDO
R/W 1 *LDO Output voltage monitoring method for PGOOD signal:
0 - Only undervoltage monitoring
1 - Overvoltage and undervoltage monitoring.
4PGOOD_
WINDOW_BUCK
R/W 1 *Buck Output voltage monitoring method for PGOOD signal:
0 - Only undervoltage monitoring
1 - Overvoltage and undervoltage monitoring.
3EN_PGOOD_LDO1R/W 0 *PGOOD signal source control from LDO1
0 - LDO1 is not monitored
1 - LDO1 Power-Good threshold voltage monitored
2EN_PGOOD_LDO0R/W 1 *PGOOD signal source control from LDO0
0 - LDO0 is not monitored
1 - LDO0 Power-Good threshold voltage monitored
1EN_PGOOD_BUCK1R/W 1 *PGOOD signal source control from Buck1
0 - Buck1 is not monitored
1 - Buck1 Power-Good threshold voltage monitored
0EN_PGOOD_BUCK0R/W 1 *PGOOD signal source control from Buck0
0 - Buck0 is not monitored
1 - Buck0 Power-Good threshold voltage monitored

PGOOD_CTRL_2

Address: 0x16

D7D6D5D4D3D2D1D0
ReservedEN_PGOOD_TWARNPG_FAULT_GATES_PGOODPGOOD_MODE
BitsFieldTypeDefaultDescription
7:3ReservedR/W0 0000
2EN_PGOOD_TWARNR/W 1 *Thermal warning control for PGOOD signal:
0 - Thermal warning not monitored
1 - PGOOD inactive if thermal warning flag is active.
1PG_FAULT_GATES_PGOODR/W 0 *Type of operation for PGOOD signal:
0 - Indicates live status of monitored voltage outputs.
1 - Indicates status of PG_FAULT register, inactive when at least one PG_FAULT_x bit is inactive.
0PGOOD_MODER/W 0 *Operating mode for PGOOD signal:
0 - Gated mode
1 - Continuous mode

PG_FAULT

Address: 0x17

D7D6D5D4D3D2D1D0
ReservedPG_FAULT_LDO1PG_FAULT_LDO0PG_FAULT_BUCK1PG_FAULT_BUCK0
BitsFieldTypeDefaultDescription
7:4ReservedR/W0000
3PG_FAULT_LDO1R/W0Source for PGOOD inactive signal:
0 - LDO1 has not set PGOOD signal inactive.
1 - LDO1 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit can be cleared by writing '1' to this bit when LDO1 output is valid.
2PG_FAULT_LDO0R/W0Source for PGOOD inactive signal:
0 - LDO0 has not set PGOOD signal inactive.
1 - LDO0 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit can be cleared by writing '1' to this bit when LDO0 output is valid.
1PG_FAULT_BUCK1R/W0Source for PGOOD inactive signal:
0 - Buck1 has not set PGOOD signal inactive.
1 - Buck1 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit can be cleared by writing '1' to this bit when Buck1 output is valid.
0PG_FAULT_BUCK0R/W0Source for PGOOD inactive signal:
0 - Buck0 has not set PGOOD signal inactive.
1 - Buck0 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit can be cleared by writing '1' to this bit when Buck0 output is valid.

RESET

Address: 0x18

D7D6D5D4D3D2D1D0
ReservedSW_RESET
BitsFieldTypeDefaultDescription
7:1ReservedR/W000 0000
0SW_RESETR/W0Software commanded reset. When written to 1, the registers will be reset to default values, OTP memory is read, and the I2C interface is reset.
The bit is automatically cleared.

INT_TOP_1

Address: 0x19

D7D6D5D4D3D2D1D0
PGOOD_INTLDO_INTBUCK_INTSYNC_CLK_INTTDIE_SD_INTTDIE_WARN_INTOVP_INTI_MEAS_INT
BitsFieldTypeDefaultDescription
7PGOOD_INTR/W0 Latched status bit indicating that the PGOOD pin has changed from active to inactive.
Write 1 to clear interrupt.
6LDO_INTR0Interrupt indicating that LDO1 and/or LDO0 have a pending interrupt. The reason for the interrupt is indicated in INT_LDO register.
This bit is cleared automatically when INT_LDO register is cleared to 0x00.
5BUCK_INTR0Interrupt indicating that Buck1 and/or Buck0 have a pending interrupt. The reason for the interrupt is indicated in INT_BUCK register.
This bit is cleared automatically when INT_BUCK register is cleared to 0x00.
4SYNC_CLK_INTR/W0Latched status bit indicating that the external clock has appeared or disappeared.
Write 1 to clear interrupt.
3TDIE_SD_INTR/W0Latched status bit indicating that the die junction temperature has exceeded the thermal shutdown level. The regulators have been disabled if they were enabled and GPO and GPO2 signals are driven low. The regulators cannot be enabled if this bit is active. The actual status of the thermal shutdown is indicated by TDIE_SD_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
2TDIE_WARN_INTR/W0Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TDIE_WARN_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
1OVP_INTR/W0Latched status bit indicating that the input voltage has exceeded the over-voltage detection level. The regulators have been disabled if they were enabled and GPO and GPO2 signals are driven low. The actual status of the over-voltage is indicated by OVP_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
0I_MEAS_INTR/W0Latched status bit indicating that the load current measurement result is available in I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt.

INT_TOP_2

Address: 0x1A

D7D6D5D4D3D2D1D0
ReservedRESET_REG_INT
BitsFieldTypeDefaultDescription
7:1ReservedR/W000 0000
0RESET_REG_INTR/W0Latched status bit indicating that either VANA supply voltage has been below undervoltage threshold level or the host has requested a reset using SW_RESET bit in RESET register. The regulators have been disabled, and registers are reset to default values and the normal startup procedure is done.
Write 1 to clear interrupt.

INT_BUCK

Address: 0x1B

D7D6D5D4D3D2D1D0
ReservedBUCK1_PG
_INT
BUCK1_SC
_INT
BUCK1_ILIM
_INT
ReservedBUCK0_PG
_INT
BUCK0_SC
_INT
BUCK0_ILIM
_INT
BitsFieldTypeDefaultDescription
7ReservedR/W0
6BUCK1_PG_INTR/W0Latched status bit indicating that Buck1 Power-Good event has been detected.
Write 1 to clear.
5BUCK1_SC_INTR/W0Latched status bit indicating that the Buck1 output voltage has been over 1 ms below short-circuit threshold level.
Write 1 to clear.
4BUCK1_ILIM_INTR/W0Latched status bit indicating that the Buck1 output current limit has been active.
Write 1 to clear.
3ReservedR/W0
2BUCK0_PG_INTR/W0Latched status bit indicating that Buck0 Power-Good event has been detected.
Write 1 to clear.
1BUCK0_SC_INTR/W0Latched status bit indicating that the Buck0 output voltage has been over 1 ms below short-circuit threshold level.
Write 1 to clear.
0BUCK0_ILIM_INTR/W0Latched status bit indicating that the Buck0 output current limit has been active.
Write 1 to clear.

INT_LDO

Address: 0x1C

D7D6D5D4D3D2D1D0
ReservedLDO1_PG
_INT
LDO1_SC
_INT
LDO1_ILIM
_INT
ReservedLDO0_PG
_INT
LDO0_SC
_INT
LDO0_ILIM
_INT
BitsFieldTypeDefaultDescription
7ReservedR/W0
6LDO1_PG_INTR/W0Latched status bit indicating that LDO1 Power-Good event has been detected.
Write 1 to clear.
5LDO1_SC_INTR/W0Latched status bit indicating that the LDO1 output voltage has been over 1 ms below short-circuit threshold level.
Write 1 to clear.
4LDO1_ILIM_INTR/W0Latched status bit indicating that the LDO1 output current limit has been active.
Write 1 to clear.
3ReservedR/W0
2LDO0_PG_INTR/W0Latched status bit indicating that LDO0 Power-Good event has been detected.
Write 1 to clear.
1LDO0_SC_INTR/W0Latched status bit indicating that the LDO0 output voltage has been over 1 ms below short-circuit threshold level.
Write 1 to clear.
0LDO0_ILIM_INTR/W0Latched status bit indicating that the LDO0 output current limit has been active.
Write 1 to clear.

TOP_STAT

Address: 0x1D

D7D6D5D4D3D2D1D0
PGOOD_STATReservedSYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_WARN
_STAT
OVP_STATReserved
BitsFieldTypeDefaultDescription
7PGOOD_STATR0Status bit indicating the status of PGOOD pin:
0 - PGOOD pin is inactive
1 - PGOOD pin is active
6:5ReservedR00
4SYNC_CLK_STATR0Status bit indicating the status of external clock (CLKIN):
0 - External clock frequency is valid
1 - External clock frequency is not valid.
3TDIE_SD_STATR0Status bit indicating the status of thermal shutdown:
0 - Die temperature below thermal shutdown level
1 - Die temperature above thermal shutdown level.
2TDIE_WARN
_STAT
R0Status bit indicating the status of thermal warning:
0 - Die temperature below thermal warning level
1 - Die temperature above thermal warning level.
1OVP_STATR0Status bit indicating the status of input overvoltage monitoring:
0 - Input voltage below overvoltage threshold level
1 - Input voltage above overvoltage threshold level.
0ReservedR0

BUCK_STAT

Address: 0x1E

D7D6D5D4D3D2D1D0
BUCK1_STATBUCK1_PG
_STAT
ReservedBUCK1_ILIM
_STAT
BUCK0_STATBUCK0_PG
_STAT
ReservedBUCK0_ILIM
_STAT
BitsFieldTypeDefaultDescription
7BUCK1_STATR0Status bit indicating the enable/disable status of Buck1:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled.
6BUCK1_PG_STATR0Status bit indicating Buck1 output voltage validity (raw status)
0 - Buck1 output voltage is valid.
1 - Buck1 output voltage is invalid.
5ReservedR0
4BUCK1_ILIM
_STAT
R0Status bit indicating Buck1 current limit status (raw status)
0 - Buck1 output current is below current limit level
1 - Buck1 output current limit is active.
3BUCK0_STATR0Status bit indicating the enable/disable status of Buck0:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled.
2BUCK0_PG_STATR0Status bit indicating Buck0 output voltage validity (raw status)
0 - Buck0 output voltage is valid.
1 - Buck0 output voltage is invalid.
1ReservedR0
0BUCK0_ILIM
_STAT
R0Status bit indicating Buck0 current limit status (raw status)
0 - Buck0 output current is below current limit level
1 - Buck0 output current limit is active.

LDO_STAT

Address: 0x1F

D7D6D5D4D3D2D1D0
LDO1_STATLDO1_PG
_STAT
ReservedLDO1_ILIM
_STAT
LDO0_STATLDO0_PG
_STAT
ReservedLDO0_ILIM
_STAT
BitsFieldTypeDefaultDescription
7LDO1_STATR0Status bit indicating the enable/disable status of LDO1:
0 - LDO1 regulator is disabled
1 - LDO1 regulator is enabled.
6LDO1_PG_STATR0Status bit indicating LDO1 output voltage validity (raw status)
0 - LDO1 output voltage is valid.
1 - LDO1 output voltage is invalid.
5ReservedR0
4LDO1_ILIM
_STAT
R0Status bit indicating LDO1 current limit status (raw status)
0 - LDO1 output current is below current limit level
1 - LDO1 output current limit is active.
3LDO0_STATR0Status bit indicating the enable/disable status of LDO0:
0 - LDO0 regulator is disabled
1 - LDO0 regulator is enabled.
2LDO0_PG_STATR0Status bit indicating LDO0 output voltage validity (raw status)
0 - LDO0 output voltage is valid.
1 - LDO0 output voltage is invalid.
1ReservedR0
0LDO0_ILIM
_STAT
R0Status bit indicating LDO0 current limit status (raw status)
0 - LDO0 output current is below current limit level
1 - LDO0 output current limit is active.

TOP_MASK_1

Address: 0x20

D7D6D5D4D3D2D1D0
PGOOD_INT_MASKReservedSYNC_CLK
_MASK
ReservedTDIE_WARN
_MASK
ReservedI_LOAD_
READY_MASK
BitsFieldTypeDefaultDescription
7PGOOD_INT
_MASK
R/W 1 *Masking for Power-Good interrupt (PGOOD_INT in INT_TOP_1 register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect PGOOD_STAT status bit in TOP_STAT register.
6:5ReservedR/W00
4SYNC_CLK
_MASK
R/W 1 *Masking for external clock detection interrupt (SYNC_CLK_INT in INT_TOP_1 register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect SYNC_CLK_STAT status bit in TOP_STAT register.
3ReservedR/W0
2TDIE_WARN
_MASK
R/W 0 *Masking for thermal warning interrupt (TDIE_WARN_INT in INT_TOP_1 register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect TDIE_WARN_STAT status bit in TOP_STAT register.
1ReservedR/W0
0I_MEAS
_MASK
R/W 0 *Masking for load current measurement ready interrupt (MEAS_INT in INT_TOP_1 register).
0 - Interrupt generated
1 - Interrupt not generated.

TOP_MASK_2

Address: 0x21

D7D6D5D4D3D2D1D0
ReservedRESET_REG
_MASK
BitsFieldTypeDefaultDescription
7:1ReservedR/W000 0000
0RESET_REG
_MASK
R/W 1 *Masking for register reset interrupt (RESET_REG_INT in INT_TOP_2 register):
0 - Interrupt generated
1 - Interrupt not generated.
This change of this bit by I2C writing has no effect because it will be read from OTP memory during reset.

BUCK_MASK

Address: 0x22

D7D6D5D4D3D2D1D0
BUCK1_PGF
_MASK
BUCK1_PGR
_MASK
ReservedBUCK1_ILIM
_MASK
BUCK0_PGF
_MASK
BUCK0_PGR
_MASK
ReservedBUCK0_ILIM
_MASK
BitsFieldTypeDefaultDescription
7BUCK1_PGF_MASKR/W 1 *Masking of Power Good invalid detection for Buck1 power good interrupt (BUCK1_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register.
6BUCK1_PGR_MASKR/W 1 *Masking of Power Good valid detection for Buck1 Power Good interrupt (BUCK1_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register.
5ReservedR0
4BUCK1_ILIM
_MASK
R/W 0 *Masking for Buck1 current limit detection interrupt (BUCK1_ILIM_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK1_ILIM_STAT status bit in BUCK_STAT register.
3BUCK0_PGF_MASKR/W 1 *Masking of Power Good invalid detection for Buck0 power good interrupt (BUCK0_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register.
2BUCK0_PGR_MASKR/W 1 *Masking of Power Good valid detection for Buck0 power good interrupt (BUCK0_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register.
1ReservedR0
0BUCK0_ILIM
_MASK
R/W 0 *Masking for Buck0 current limit detection interrupt (BUCK0_ILIM_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK0_ILIM_STAT status bit in BUCK_STAT register.

LDO_MASK

Address: 0x23

D7D6D5D4D3D2D1D0
LDO1_PGF
_MASK
LDO1_PGR
_MASK
ReservedLDO1_ILIM
_MASK
LDO0_PGF
_MASK
LDO0_PGR
_MASK
ReservedLDO0_ILIM
_MASK
BitsFieldTypeDefaultDescription
7LDO1_PGF_MASKR/W 0 *Masking of Power Good invalid detection for LDO1 power good interrupt (LDO1_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO1_PG_STAT status bit in LDO_STAT register.
6LDO1_PGR_MASKR/W 0 *Masking of Power Good valid detection for LDO1 power good interrupt (LDO1_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO1_PG_STAT status bit in LDO_STAT register.
5ReservedR0
4LDO1_ILIM
_MASK
R/W 0 *Masking for LDO1 current limit detection interrupt (LDO1_ILIM_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO1_ILIM_STAT status bit in LDO_STAT register.
3LDO0_PGF_MASKR/W 1 *Masking of Power Good invalid detection for LDO0 power good interrupt (LDO0_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO0_PG_STAT status bit in LDO_STAT register.
2LDO0_PGR_MASKR/W 1 *Masking of Power Good valid detection for LDO0 power good interrupt (LDO0_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO0_PG_STAT status bit in LDO_STAT register.
1ReservedR0
0LDO0_ILIM
_MASK
R/W 0 *Masking for LDO0 current limit detection interrupt (LDO0_ILIM_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO0_ILIM_STAT status bit in LDO_STAT register.

SEL_I_LOAD

Address: 0x24

D7D6D5D4D3D2D1D0
ReservedLOAD_CURRENT_BUCK
_SELECT
BitsFieldTypeDefaultDescription
7:1ReservedR/W000 0000
0LOAD_CURRENT_
BUCK_SELECT
R/W0Start the current measurement on the selected regulator:
0 - Buck0
1 - Buck1
The measurement is started when register is written.

I_LOAD_2

Address: 0x25

D7D6D5D4D3D2D1D0
ReservedBUCK_LOAD_CURRENT[8]
BitsFieldTypeDefaultDescription
7:1ReservedR000 0000
0BUCK_LOAD_
CURRENT[8]
R0This register describes the MSB bit of the average load current on selected regulator with a resolution of 20 mA per LSB and maximum 10.22-A current.

I_LOAD_1

Address: 0x26

D7D6D5D4D3D2D1D0
BUCK_LOAD_CURRENT[7:0]
BitsFieldTypeDefaultDescription
7:0BUCK_LOAD_
CURRENT[7:0]
R0000 0000This register describes 8 LSB bits of the average load current on selected regulator with a resolution of 20 mA per LSB and maximum 10.22-A current.