ZHCSGT4 September 2017 LP87332A-Q1

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6I2C Serial Bus Timing Parameters
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 DC-DC Converters
        1. 7.3.1.1Overview
        2. 7.3.1.2Transition Between PWM and PFM Modes
        3. 7.3.1.3Buck Converter Load Current Measurement
        4. 7.3.1.4Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4 Power-Up
      5. 7.3.5 Regulator Control
        1. 7.3.5.1Enabling and Disabling Regulators
        2. 7.3.5.2Changing Output Voltage
      6. 7.3.6 Enable and Disable Sequences
      7. 7.3.7 Device Reset Scenarios
      8. 7.3.8 Diagnosis and Protection Features
        1. 7.3.8.1Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1PGOOD Pin Gated mode
          2. 7.3.8.1.2PGOOD Pin Continuous Mode
        2. 7.3.8.2Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1Output Power Limit
          2. 7.3.8.2.2Thermal Warning
        3. 7.3.8.3Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2Overvoltage Protection
          3. 7.3.8.3.3Thermal Shutdown
        4. 7.3.8.4Fault (Power Down)
          1. 7.3.8.4.1Undervoltage Lockout
      9. 7.3.9 Operation of the GPO Signals
      10. 7.3.10Digital Signal Filtering
    4. 7.4Device Functional Modes
      1. 7.4.1Modes of Operation
    5. 7.5Programming
      1. 7.5.1I2C-Compatible Interface
        1. 7.5.1.1Data Validity
        2. 7.5.1.2Start and Stop Conditions
        3. 7.5.1.3Transferring Data
        4. 7.5.1.4I2C-Compatible Chip Address
        5. 7.5.1.5Auto-Increment Feature
    6. 7.6Register Maps
      1. 7.6.1Register Descriptions
        1. 7.6.1.1 DEV_REV
        2. 7.6.1.2 OTP_REV
        3. 7.6.1.3 BUCK0_CTRL_1
        4. 7.6.1.4 BUCK0_CTRL_2
        5. 7.6.1.5 BUCK1_CTRL_1
        6. 7.6.1.6 BUCK1_CTRL_2
        7. 7.6.1.7 BUCK0_VOUT
        8. 7.6.1.8 BUCK1_VOUT
        9. 7.6.1.9 LDO0_CTRL
        10. 7.6.1.10LDO1_CTRL
        11. 7.6.1.11LDO0_VOUT
        12. 7.6.1.12LDO1_VOUT
        13. 7.6.1.13BUCK0_DELAY
        14. 7.6.1.14BUCK1_DELAY
        15. 7.6.1.15LDO0_DELAY
        16. 7.6.1.16LDO1_DELAY
        17. 7.6.1.17GPO_DELAY
        18. 7.6.1.18GPO2_DELAY
        19. 7.6.1.19GPO_CTRL
        20. 7.6.1.20CONFIG
        21. 7.6.1.21PLL_CTRL
        22. 7.6.1.22PGOOD_CTRL_1
        23. 7.6.1.23PGOOD_CTRL_2
        24. 7.6.1.24PG_FAULT
        25. 7.6.1.25RESET
        26. 7.6.1.26INT_TOP_1
        27. 7.6.1.27INT_TOP_2
        28. 7.6.1.28INT_BUCK
        29. 7.6.1.29INT_LDO
        30. 7.6.1.30TOP_STAT
        31. 7.6.1.31BUCK_STAT
        32. 7.6.1.32LDO_STAT
        33. 7.6.1.33TOP_MASK_1
        34. 7.6.1.34TOP_MASK_2
        35. 7.6.1.35BUCK_MASK
        36. 7.6.1.36LDO_MASK
        37. 7.6.1.37SEL_I_LOAD
        38. 7.6.1.38I_LOAD_2
        39. 7.6.1.39I_LOAD_1
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
        1. 8.2.1.1Inductor Selection
        2. 8.2.1.2Buck Input Capacitor Selection
        3. 8.2.1.3Buck Output Capacitor Selection
        4. 8.2.1.4LDO Input Capacitor Selection
        5. 8.2.1.5LDO Output Capacitor Selection
      2. 8.2.2Detailed Design Procedure
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11器件和文档支持
    1. 11.1器件支持
      1. 11.1.1Third-Party Products Disclaimer
    2. 11.2接收文档更新通知
    3. 11.3社区资源
    4. 11.4商标
    5. 11.5静电放电警告
    6. 11.6Glossary
  12. 12机械、封装和可订购信息

Specifications

Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1) (2)
MINMAXUNIT
VIN_Bx, VANAVoltage on power connections (must use the same input supply)–0.36V
VIN_LDOxVoltage on power connections–0.36V
SW_BxVoltage on buck switch nodes–0.3(VIN_Bx + 0.3 V) with 6-V maximumV
FB_BxVoltage on buck voltage sense nodes–0.3(VANA + 0.3 V) with 6-V maximumV
VOUT_LDOxVoltage on LDO output-0.3(VIN_LDOx + 0.3 V) with 6-V maximumV
SDA, SCL, nINT, ENVoltage on logic pins (input or output pins)–0.36V
PGOOD, GPO, CLKIN (GPO2)Voltage on logic pins (input or output pins)–0.3(VANA + 0.3 V) with 6-V maximumV
TJ-MAX Junction temperature−40150°C
Tstg Storage temperature–65150
Maximum lead temperature (soldering, 10 seconds)260
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground.

ESD Ratings

VALUEUNIT
V(ESD) Electrostatic dischargeHuman-body model (HBM), per AEC Q100-002(1) ±2000V
Charged-device model (CDM), per AEC Q100-011All pins±500
Corner pins (1, 7, 8, 14, 15, 21, 22, 28)±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINMAXUNIT
INPUT VOLTAGE
VIN_Bx, VANAVoltage on power connections (must use the same input supply)2.8 5.5V
VIN_LDOxVoltage on LDO inputs2.5 5.5V
EN, nINTVoltage on logic pins (input or output pins)05.5V
CLKINVoltage on logic pins (input pin)0VANA with 5.5-V maximumV
PGOOD, GPO, GPO2Voltage on logic pins (output pins)0VANAV
SCL, SDAVoltage on I2C interface, Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes01.95V
Voltage on I2C interface, Standard (100 kHz), Fast (400 kHz), and Fast+ (1 MHz) Modes0VANA with 3.6-V maximumV
TEMPERATURE
TJ Junction temperature−40140°C
TA Ambient temperature−40125°C

Thermal Information

THERMAL METRIC(1) LP87332A-Q1UNIT
RHD (VQFN)
28 PINS
RθJA Junction-to-ambient thermal resistance 36.7°C/W
RθJCtop Junction-to-case (top) thermal resistance 26.6°C/W
RθJB Junction-to-board thermal resistance 8.9°C/W
ψJT Junction-to-top characterization parameter 0.4°C/W
ψJB Junction-to-board characterization parameter 8.8°C/W
RθJCbot Junction-to-case (bottom) thermal resistance 2.2°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V, unless otherwise noted(1) (2).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
EXTERNAL COMPONENTS
CIN_BUCK Input filtering capacitance for buck regulatorsEffective capacitance, connected from VIN_Bx to PGND_Bx 1.910µF
COUT_BUCK Output filtering capacitance for buck regulatorsEffective capacitance1022500µF
CPOL_BUCK Point-of-load (POL) capacitance for buck regulatorsOptional POL capacitance22µF
COUT-TOTAL_BUCK Buck output capacitance, total (local and POL)Total output capacitance500µF
CIN_LDO Input filtering capacitance for LDO regulatorsEffective capacitance, connected from VIN_LDOx to AGND. CIN_LDO must be at least two times larger than COUT_LDO 0.62.2µF
COUT_LDO Output filtering capacitance for LDO regulatorsEffective capacitance0.412.7µF
ESRC Input and output capacitor ESR[1-10] MHz210
LInductorInductance of the inductor0.47µH
–30%30%
DCRL Inductor DCR25
BUCK REGULATORS
V(VIN_Bx), V(VANA) Input voltage rangeVIN_Bx and VANA pins must be connected to the same supply line2.83.75.5V
VOUT_Bx Output voltageProgrammable voltage range0.713.36V
Step size, 0.7 V ≤ VOUT < 0.73 V10mV
Step size, 0.73 V ≤ VOUT < 1.4 V5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V20
IOUT_Bx Output currentOutput current3(3) A
Input and Output voltage differenceMinimum voltage between V(VIN_Bx) and VOUT to fulfill the electrical characteristics0.8V
VOUT_Bx_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperatureForce PWM mode, VOUT < 1 V–20 20 mV
Force PWM mode, VOUT ≥ 1 V–2%2%
PFM mode, VOUT < 1 V, the average output voltage level is increased by max. 20 mV–20mV40mVmV
PFM mode, VOUT ≥ 1 V, the average output voltage level is increased by max. 20 mV–2%2% + 20 mV
Ripple voltagePWM mode, L = 0.47 µH10mVp-p
PFM mode, L = 0.47 µH25
DCLNR DC line regulationIOUT = 1 A±0.05%/V
DCLDR DC load regulation in PWM modeVOUT_Bx = 1 V, IOUT from 0 to IOUT(max) 0.3%
TLDSR Transient load step responseIOUT = 0.1 A to 2 A, TR = TF = 400 ns, PWM mode±55mV
TLNSR Transient line responseV(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) ±10mV
ILIM FWD Forward current limit for both bucks (peak for every switching cycle)Programmable range1.54A
Step size0.5
Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 4 A–5% 7.5%20%
Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A–20% 7.5%20%
ILIM NEG Negative current limit1.62.03.0A
RDS(ON) HS FET On-resistance, high-side FETEach phase, between VIN_Bx and SW_Bx pins (I = 1 A)50110
RDS(ON) LS FET On-resistance, low-side FETEach phase, between SW_Bx and PGND_Bx pins (I = 1 A)4590
ƒSW Switching frequencyPWM mode1.822.2MHz
Start-up time (soft start)From ENx to VOUT_Bx = 0.35 V (slew-rate control begins)120µs
Output voltage slew-rate(4) SLEW_RATEx[2:0] = 010, COUT-TOTAL_BUCK < 80 µF–15%1015%mV/µs
SLEW_RATEx[2:0] = 011, COUT-TOTAL_BUCK < 130 µF7.5
SLEW_RATEx[2:0] = 100, COUT-TOTAL_BUCK < 250 µF3.8
SLEW_RATEx[2:0] = 101, COUT-TOTAL_BUCK < 500 µF1.9
SLEW_RATEx[2:0] = 110, COUT-TOTAL_BUCK < 500 µF0.94
SLEW_RATEx[2:0] = 111, COUT-TOTAL_BUCK < 500 µF0.47
IPFM-PWM PFM-to-PWM - current threshold(5) 550mA
IPWM-PFM PWM-to-PFM - current threshold(5) 290mA
RDIS_Bx Output pull-down resistanceRegulator disabled150250350Ω
Output voltage monitoring for PGOOD pin and for Powergood InterruptV(VIN_Bx) and V(VANA) fixed 3.7 V
Overvoltage threshold (compared to DC output voltage level, VVOUT_Bx_DC)395064mV
Undervoltage threshold (compared to DC output voltage level, VVOUT_Bx_DC)–53–40–29
Deglitch time during operation and after voltage change415µs
Gating time for PGOOD signal after regulator enable or voltage changePGOOD_MODE = 0800µs
LDO REGULATORS
VIN_LDOx Input voltage range for LDO power inputsVIN_LDOx can be higher or lower than V(VANA) 2.53.75.5V
VOUT_LDOx Output voltageProgrammable voltage range0.83.3V
Step size0.1
IOUT_LDOx Output current300mA
Dropout voltageV(VIN_LDOx) – V(VOUT_LDOx), IOUT = IOUT(max), Programmed output voltage is higher than V(VIN_LDOx) 200mV
VOUT_LDO_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process, temperatureVOUT < 1 V–20 20 mV
VOUT ≥ 1 V–2%2%
DCLNR DC line regulationIOUT = 1 mA0.1%/V
DCLDR DC load regulationIOUT = 1 mA to IOUT(max) 0.8%
TLDSR Transient load step responseIOUT = 1 mA to 300 mA, TR = TF = 1 µs–50/+40mV
TLNSR Transient line responseV(VIN_LDOx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) ±7mV
PSRRPower supply ripple rejectionƒ = 10 kHz, IOUT = IOUT(max) 53dB
Noise10 Hz < F < 100 kHz, IOUT = IOUT(max) 82µVrms
ISHORT(LDOx) LDO current limitVOUT = 0 V400500600mA
Start-up timeFrom enable to valid output voltage300µs
Slew rate during start-up15mV/µs
RDIS_LDOx Output pulldown resistanceRegulator disabled150250350Ω
Output voltage monitoring for PGOOD pin and for power-good interruptOvervoltage monitoring, voltage rising (compared to DC output voltage level, VOUT_LDO_DC)106%108%110%
Overvoltage monitoring, hysteresis3%3.5%4%
Undervoltage monitoring, voltage falling (compared to DC output voltage level, VOUT_LDO_DC)90%92%94%
Undervoltage monitoring, hysteresis3%3.5%4%
Deglitch time during operation and after voltage change415µs
Gating time for PGOOD signal after regulator enable or voltage changePGOOD_MODE = 0800µs
EXTERNAL CLOCK AND PLL
fEXT_CLK External input clock(6) Nominal frequency124MHz
Nominal frequency step size1
Required accuracy from nominal frequency–30%10%
External clock detectionDelay for missing clock detection1.8µs
Delay and debounce for clock detection20
Clock change delay (internal to external)Delay from valid clock detection to use of external clock600µs
PLL output clock jitterCycle to cycle300ps, p-p
PROTECTION FUNCTIONS
Thermal warningTemperature rising, TDIE_WARN_LEVEL = 0115125135°C
Temperature rising, TDIE_WARN_LEVEL = 1127137147
Hysteresis20
Thermal shutdownTemperature rising140150160°C
Hysteresis20
VANAOVP VANA overvoltage Voltage rising5.65.86.1V
Voltage falling5.455.735.96
Hysteresis40mV
VANAUVLO VANA undervoltage lockoutVoltage rising2.512.632.75V
Voltage falling2.52.62.7
Buck short-circuit detectionThreshold280360440mV
LDO short-circuit detectionThreshold190300450mV
LOAD CURRENT MEASUREMENT FOR BUCK REGULATORS
Current measurement rangeMaximum code10.22A
ResolutionLSB20mA
Measurement accuracyIOUT > 1 A<10%
Measurement timePFM mode (automatically changing to PWM mode for the measurement)45µs
PWM mode4
CURRENT CONSUMPTION
Standby current consumption, regulators disabled9µA
Active current consumption, one buck regulator enabled in Auto mode, internal RC oscillator, PGOOD monitoring enabledIOUT_Bx = 0 mA, not switching58µA
Active current consumption, two buck regulators enabled in Auto mode, internal RC oscillator, PGOOD monitoring enabledIOUT_Bx = 0 mA, not switching100µA
Active current consumption during PWM operation, one buck regulator enabledIOUT_Bx = 0 mA15mA
Active current consumption during PWM operation, two buck regulators enabledIOUT_Bx = 0 mA30mA
LDO regulator enabledAdditional current consumption per LDO, IOUT_LDOx = 0 mA86µA
PLL and clock detector current consumptionfEXT_CLK = 1 MHz, Additional current consumption when enabled2mA
DIGITAL INPUT SIGNALS EN, SCL, SDA, CLKIN
VIL Input low level0.4V
VIH Input high level1.2
VHYS Hysteresis of Schmitt Trigger inputs1080200mV
EN/CLKIN pulldown resistanceEN_PD/CLKIN_PD = 1500
DIGITAL OUTPUT SIGNALS nINT, SDA
VOL Output low levelnINT: ISOURCE = 2 mA0.4V
SDA: ISOURCE = 20 mA0.4V
RP External pullup resistor for nINTTo VIO Supply 10
DIGITAL OUTPUT SIGNALS PGOOD, GPO, GPO2
VOL Output low levelISOURCE = 2 mA0.4V
VOH Output high level, configured to push-pullISINK = 2 mAVVANA – 0.4VVANA V
VPU Supply voltage for external pull-up resistor, configured to open-drainVVANA V
RPU External pull-up resistor, configured to open-drain10
ALL DIGITAL INPUTS
ILEAK Input currentAll logic inputs over pin voltage range−11µA
All voltage values are with respect to network ground.
Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely norm.
The maximum output current can be limited by the forward current limit ILIM FWD. The power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.
The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current.
The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage and the inductor current level.
The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.

I2C Serial Bus Timing Parameters

These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V. See (1) and Figure 1.
MINMAXUNIT
fSCL Serial clock frequencyStandard mode100kHz
Fast mode400
Fast mode+1MHz
High-speed mode, Cb = 100 pF3.4
High-speed mode, Cb = 400 pF1.7
tLOW SCL low timeStandard mode4.7µs
Fast mode1.3
Fast mode+0.5
High-speed mode, Cb = 100 pF0.16
High-speed mode, Cb = 400 pF0.32
tHIGH SCL high timeStandard mode4µs
Fast mode0.6
Fast mode+0.26
High-speed mode, Cb = 100 pF0.06
High-speed mode, Cb = 400 pF0.12
tSU;DAT Data setup timeStandard mode250ns
Fast mode100
Fast mode+50
High-speed mode10
tHD;DAT Data hold timeStandard mode103450ns
Fast mode10900
Fast mode+10
High-speed mode, Cb = 100 pF1070
High-speed mode, Cb = 400 pF10150
tSU;STA Setup time for a start or a repeated start conditionStandard mode4.7µs
Fast mode0.6
Fast mode+0.26
High-speed mode0.16
tHD;STA Hold time for a start or a repeated start conditionStandard mode4µs
Fast mode0.6
Fast mode+0.26
High-speed mode0.16
tBUF Bus free time between a stop and start conditionStandard mode4.7µs
Fast mode1.3
Fast mode +0.5
tSU;STO Setup time for a stop conditionStandard mode4µs
Fast mode0.6
Fast mode+0.26
High-speed mode0.16
trDA Rise time of SDA signalStandard mode1000ns
Fast mode20300
Fast mode+120
High-speed mode, Cb = 100 pF1080
High-speed mode, Cb = 400 pF20160
tfDA Fall time of SDA signalStandard mode300ns
Fast mode20 × (VDD / 5.5 V)300
Fast mode+20 × (VDD / 5.5 V)​​​​​​​120
High-speed mode, Cb = 100 pF1080
High-speed mode, Cb = 400 pF30160
trCL Rise time of SCL signalStandard mode1000ns
Fast mode20300
Fast mode+120
High-speed mode, Cb = 100 pF1040
High-speed mode, Cb = 400 pF2080
trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bitHigh-speed mode, Cb = 100 pF1080ns
High-speed mode, Cb = 400 pF20160
tfCL Fall time of a SCL signalStandard mode300ns
Fast mode20 × (VDD / 5.5 V)300
Fast mode +20 × (VDD / 5.5 V)120
High-speed mode, Cb = 10 – 100 pF1040
High-speed mode, Cb = 400 pF2080
Cb Capacitive load for each bus line (SCL and SDA)400pF
tSP Pulse width of spike suppressed (SCL and SDA spikes that are less then the indicated width are suppressed)Standard mode, fast mode, and fast mode+50ns
High-speed mode10
Cb refers to the capacitance of one bus line.
LP87332A-Q1 30190619.gif Figure 1. I2C Timing

Typical Characteristics

Unless otherwise specified: V(VIN_Bx) = V(VIN_LDOx) = V(VANA) = 3.7 V, VOUT_Bx = 1 V, VOUT_LDO = 1 V, TA = 25°C, L = 0.47 µH (TOKO DFE252012PD-R47M), COUT_BUCK = 22 µF, CPOL_BUCK = 22 µF, and COUT_LDO = 1 µF.
LP87332A-Q1 D101_SNVSAB5.gif
Regulators disabled
Figure 2. Standby Current Consumption vs Input Voltage
LP87332A-Q1 D103_SNVSAB5.gif
VOUT_Bx = 1 VLoad = 0 mA
Figure 4. Active State Current Consumption vs Input Voltage, One Buck Regulator Enabled in Forced PWM Mode
LP87332A-Q1 D102_SNVSAB5.gif
VOUT_Bx = 1 VLoad = 0 mA
Figure 3. Active State Current Consumption vs Input Voltage, One Buck Regulator Enabled in PFM Mode
LP87332A-Q1 D104_SNVSAB5.gif
VOUT_LDOx = 1 VLoad = 0 mA
Figure 5. Active State Current Consumption vs Input Voltage, One LDO Regulator Enabled