SNVS482F January   2007  – December 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO)
      2. 7.3.2 Supply Sequencing
      3. 7.3.3 Reverse Voltage
      4. 7.3.4 Soft-Start
      5. 7.3.5 Setting The Output Voltage
      6. 7.3.6 Enable (EN)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Voltage
      2. 7.4.2 Bias Voltage
      3. 7.4.3 Enable (EN) Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Input Capacitor
          2. 8.2.2.1.2 Output Capacitor
          3. 8.2.2.1.3 Bias Capacitor
          4. 8.2.2.1.4 Setting the Output Voltage
          5. 8.2.2.1.5 Feed Forward Capacitor, CFF
        2. 8.2.2.2 Power Dissipation and Heat Sinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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1 Features

  • Input VIN Range 0.93 V to 5.5 V
  • Adjustable VOUT Range 0.8 V to 1.8 V
  • Wide VBIAS Supply Operating Range 3 V to 5.5 V
  • Dropout Voltage of 130 mV (Typical) at 1.5-A Load Current
  • Precision Output Voltage Across All Line and Load Conditions:
    • ±1.5% VADJ for TJ = 25°C
    • ±2% VADJ for 0°C ≤ TJ ≤ +125°C
    • ±3% VADJ for –40°C ≤ TJ ≤ +125°C
  • Overtemperature and Overcurrent Protection
  • Stable with 10-µF Ceramic Capacitors
  • Available in 7-pin TO-220, 7-Pin DDPAK/TO-263, and 8-Pin SO PowerPAD™ Packages
  • −40°C to +125°C Operating Junction Temperature Range

2 Applications

  • ASIC Power Supplies In:
    • Desktops, Notebooks, and Graphics Cards, Servers
    • Gaming Set Top Boxes, Printers and Copiers
  • Server Core and I/O Supplies
  • DSP and FPGA Power Supplies
  • SMPS Post-Regulator

3 Description

The LP38852-ADJ is a high-current, fast-response regulator which can maintain output voltage regulation with extremely low input-to-output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: VBIAS provides voltage to drive the gate of the N-MOS power transistor, while VIN is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultralow VIN voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability.

The fast transient response of this device makes it suitable for use in powering DSP, microcontroller core voltages, and switch-mode power supply post-regulators.

Dropout Voltage: 130 mV (typical) at 1.5-A load current.

Low Ground Pin Current: 10 mA (typical) at 1.5-A load current.

Soft Start: Programmable soft-start time.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LP38852-ADJ DDPAK/TO-263 (7) 10.10 mm × 8.89 mm
TO-220 (7) 14.986 × 10.16 mm
SO PowerPAD (8) 4.89 mm × 3.90 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Circuit

LP38852-ADJ 20213901.gif