ZHCSDH8 March   2015 LMX2571

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  R-Dividers and Multiplier
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  PLL N-Divider and Fractional Circuitry
      5. 7.3.5  Partially Integrated Loop Filter
      6. 7.3.6  Low-Noise, Fully Integrated VCO
      7. 7.3.7  External VCO Support
      8. 7.3.8  Programmable RF Output Divider
      9. 7.3.9  Programmable RF Output Buffer
      10. 7.3.10 Integrated TX, RX Switch
      11. 7.3.11 Powerdown
      12. 7.3.12 Lock Detect
      13. 7.3.13 FSK Modulation
      14. 7.3.14 FastLock
      15. 7.3.15 Register Readback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
      2. 7.4.2 Duplex Mode
      3. 7.4.3 FSK Mode
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1  R60 Register (offset = 3Ch) [reset = 4000h]
      2. 7.6.2  R58 Register (offset = 3Ah) [reset = C00h]
      3. 7.6.3  R53 Register (offset = 35h) [reset = 2802h]
      4. 7.6.4  R47 Register (offset = 2Fh) [reset = 0h]
      5. 7.6.5  R42 Register (offset = 2Ah) [reset = 210h]
      6. 7.6.6  R41 Register (offset = 29h) [reset = 810h]
      7. 7.6.7  R40 Register (offset = 28h) [reset = 101Ch]
      8. 7.6.8  R39 Register (offset = 27h) [reset = 11F0h]
      9. 7.6.9  R35 Register (offset = 23h) [reset = 647h]
      10. 7.6.10 R34 Register (offset = 22h) [reset = 1000h]
      11. 7.6.11 R33 Register (offset = 21h) [reset = 0h]
      12. 7.6.12 R25 to R32 Register (offset = 19h to 20h) [reset = 0h]
      13. 7.6.13 R24 Register (offset = 18h) [reset = 10h]
      14. 7.6.14 R23 Register (offset = 17h) [reset = 10A4h]
      15. 7.6.15 R22 Register (offset = 16h) [reset = 8584h]
      16. 7.6.16 R21 Register (offset = 15h) [reset = 101h]
      17. 7.6.17 R20 Register (offset = 14h) [reset = 28h]
      18. 7.6.18 R19 Register (offset = 13h) [reset = 0h]
      19. 7.6.19 R18 Register (offset = 12h) [reset = 0h]
      20. 7.6.20 R17 Register (offset = 11h) [reset = 0h]
      21. 7.6.21 R9 to R16 Register (offset = 9h to 10h) [reset = 0h]
      22. 7.6.22 R8 Register (offset = 8h) [reset = 10h]
      23. 7.6.23 R7 Register (offset = 7h) [reset = 10A4h]
      24. 7.6.24 R6 Register (offset = 6h) [reset = 8584h]
      25. 7.6.25 R5 Register (offset = 5h) [reset = 101h]
      26. 7.6.26 R4 Register (offset = 4h) [reset = 28h]
      27. 7.6.27 R3 Register (offset = 3h) [reset = 0h]
      28. 7.6.28 R2 Register (offset = 2h) [reset = 0h]
      29. 7.6.29 R1 Register (offset = 1h) [reset = 0h]
      30. 7.6.30 R0 Register (offset = 0h) [reset = 3h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Direct Digital FSK Modulation
      2. 8.1.2  Frequency and Output Port Switching with TrCtl Pin
      3. 8.1.3  OSCin Configuration
      4. 8.1.4  Register R0 F1F2_INIT, F1F2_MODE usage
      5. 8.1.5  FastLock with External VCO
      6. 8.1.6  OSCin Slew Rate
      7. 8.1.7  RF Output Buffer Power Control
      8. 8.1.8  RF Output Buffer Type
      9. 8.1.9  MULT Multiplier
      10. 8.1.10 Integrated VCO
    2. 8.2 Typical Applications
      1. 8.2.1 Synthesizer Duplex Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Synthesizer Duplex Mode Application Curves
      2. 8.2.2 PLL Duplex Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 PLL Duplex Mode Application Curves
      3. 8.2.3 Synthesizer/PLL Duplex Mode
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Synthesizer/PLL Duplex Mode Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
  • NJK|36
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

WQFN (NJK) Package
36 Pins
Top View
LMX2571 6_PinOut_SNAS654.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
Bypass1 2 Bypass Place a 100-nF capacitor to GND.
Bypass2 3 Bypass Place a 100-nF capacitor to GND.
CE 19 Input Chip Enable input. Active HIGH powers on the device.
CLK 11 Input MICROWIRE clock input.
CPout 25 Output Internal VCO charge pump access point to connect to a 2nd order loop filter.
CPoutExt 30 Output 5-V charge pump output used in PLL mode (external VCO).
DAP 0 GND The DAP should be grounded.
DATA 12 Input MICROWIRE serial data input.
Fin 24 Input High frequency AC coupled input pin for an external VCO. Leave it open or AC coupled to GND if not being used.
FSK_D0 7 Input FSK data bit 0 (FSK PIN mode) / I2S FS input (FSK I2S mode).
FSK_D1 6 Input FSK data bit 1 (FSK PIN mode) / I2S DATA input (FSK I2S mode).
FSK_D2 5 Input FSK data bit 2 (FSK PIN mode).
FSK_DV 4 Input FSK data valid input (FSK PIN mode) / I2S CLK input (FSK I2S mode).
FLout1 29 Output FastLock output control 1 for external switch. Output is HIGH when F1 is selected.
FLout2 28 Output FastLock output control 2 for external switch. Output is HIGH when F2 is selected.
GND 23 GND VCO ground.
GND 31 GND Charge pump ground.
GND 35 GND OSCin ground.
LE 13 Input MICROWIRE latch enable input.
MUXout 10 Output Multiplexed output that can be assigned to lock detect or readback serial data output.
NC 8,14, 26 NC Do not connect these pins.
OSCin 34 Input Reference clock input.
OSCin* 36 Input Complementary reference clock input.
RFoutRx 16 Output RF output used to drive receive mixer. Selectable open drain or push-pull output.
RFoutTx 17 Output RF output used to drive transmit signal. Selectable open drain or push-pull output.
TrCtl 18 Input Transmit/Receive control. This pin controls the RF output port and the output frequency selection.
Vcc3p3 1, 9, 20, 27 Supply Connect to 3.3-V supply.
VccIO 15, 33 Supply Supply for digital logic interface. Connect to 3.3-V supply.
VcpExt 32 Supply Supply for 5-V charge pump. Connect to 5-V supply in PLL mode. Connect to either 3.3-V or 5-V supply in synthesizer mode.
VrefVCO 22 Bypass LDO output. Place a 100-nF capacitor to GND.
VregVCO 21 Bypass Bias circuitry for the VCO. Place a 2.2-µF capacitor to GND.