ZHCSGL2B December 2016  – June 2017 LMK62A2-100M , LMK62A2-150M , LMK62A2-156M , LMK62A2-200M , LMK62A2-266M , LMK62E0-156M , LMK62E2-156M

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Supply
    6. 6.6 LVPECL Output Characteristics
    7. 6.7 LVDS Output Characteristics
    8. 6.8 HCSL Output Characteristics
    9. 6.9 OE Input Characteristics
    10. 6.10Frequency Tolerance Characteristics
    11. 6.11Power-On/Reset Characteristics (VDD)
    12. 6.12PSRR Characteristics
    13. 6.13PLL Clock Output Jitter Characteristics
    14. 6.14Additional Reliability and Qualification
  7. Parameter Measurement Information
    1. 7.1Device Output Configurations
  8. Power Supply Recommendations
  9. Layout
    1. 9.1Layout Guidelines
      1. 9.1.1Ensuring Thermal Reliability
      2. 9.1.2Best Practices for Signal Integrity
      3. 9.1.3Recommended Solder Reflow Profile
  10. 10器件和文档支持
    1. 10.1接收文档更新通知
    2. 10.2社区资源
    3. 10.3商标
    4. 10.4静电放电警告
    5. 10.5Glossary
  11. 11机械、封装和可订购信息

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VDDDevice supply voltage–0.33.6V
VINOutput voltage for logic inputs–0.3VDD + 0.3V
VOUTOutput voltage for clock outputs–0.3VDD + 0.3V
TJJunction temperature150°C
TstgStorage temperature–40125°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±2000V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
VDDDevice supply voltage3.135 3.3 3.465 V
TAAmbient temperature–40 25 85 °C
TJJunction temperature105°C
tRAMP VDD power-up ramp time0.1100ms

Thermal Information

THERMAL METRIC(1)LMK62XX (2) (3) (4)UNIT
SIA (QFM )
6 PINS
Airflow (LFM) 0
RθJAJunction-to-ambient thermal resistance 94.5°C/W
RθJC(top)Junction-to-case (top) thermal resistance 65.1°C/W
RθJBJunction-to-board thermal resistance 59°C/W
ψJTJunction-to-top characterization parameter 23.3°C/W
ψJBJunction-to-board characterization parameter 64.1°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance n/a°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
The package thermal resistance is calculated on a 4-layer JEDEC board.
Connected to GND with 2 thermal vias (0.3-mm diameter).
ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations section for more information on ensuring good system reliability and quality.

Electrical Characteristics - Power Supply(1)

VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IDDDevice current consumptionLVPECL(2)95110mA
LVDS85100
HCSL(3)90105
IDD-PDDevice current consumption when output is disabledOE = GND70mA
Refer to Parameter Measurement Information for relevant test conditions.
On-chip power dissipation should exclude 40 mW, dissipated in the 150-Ω termination resistors, from total power dissipation.
Excludes load current.

LVPECL Output Characteristics(1)

VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
fOUTOutput frequency(2)400MHz
VODOutput voltage swing (VOH – VOL)(2)7009501200mV
VOUT, DIFF, PPDifferential output peak-to-peak swing2 × |VOD|V
VOSOutput common-mode voltageVDD – 1.45V
tR / tFOutput rise/fall time (20% to 80%)(3)260350ps
ODCOutput duty cycle(3)45%55%
Refer to Parameter Measurement Information for relevant test conditions.
An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
Ensured by characterization.

LVDS Output Characteristics(1)

VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
fOUTOutput frequency(1)400MHz
VODOutput voltage swing (VOH - VOL)(1)300390480mV
VOUT, DIFF, PPDifferential output peak-to-peak swing2 x |VOD|V
VOSOutput common-mode voltage1.2V
tR / tFOutput rise/fall time (20% to 80%)(2)260350ps
ODCOutput duty cycle(2)45%55%
ROUTDifferential output impedance107Ω
An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
Ensured by characterization.

HCSL Output Characteristics(1)

VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
fOUTOutput frequency400MHz
VOHOutput high voltage660900mV
VOLOutput low voltage–100100mV
VCROSSAbsolute crossing voltage(2)(3)250475mV
VCROSS-DELTAVariation of VCROSS(2)(3)0140mV
dV/dtSlew rate(4)13V/ns
ODCOutput duty cycle(4)45%55%
Refer to Parameter Measurement Information for relevant test conditions.
Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential zero crossing.
Ensured by design.
Ensured by characterization.

OE Input Characteristics

VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VIHInput high voltage1.4V
VILInput low voltage0.6V
IIHInput high currentVIH = VDD–4040µA
IILInput low currentVIL = GND–4040µA
CINInput capacitance2pF

Frequency Tolerance Characteristics(1)

VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
fTTotal frequency tolerance LMK62X2: All output formats, frequency bands and device junction temperature up to 105°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and 5-year aging at 40°C–5050ppm
LMK62X0: All output formats, frequency bands and device junction temperature up to 105°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and 5-year aging at 40°C–2525ppm
Ensured by characterization.

Power-On/Reset Characteristics (VDD)

VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VTHRESHThreshold voltage(1)2.853V
VDROOPAllowable voltage droop(2)0.1V
tSTARTUPStart-up time (1)Time elapsed from VDD at 3.135 V to output enabled10ms
tOE-ENOutput enable time(2)Time elapsed from OE at VIH to output enabled50µs
tOE-DISOutput disable time(2)Time elapsed from OE at VIL to output disabled50µs
Ensured by characterization.
Ensured by design.

PSRR Characteristics(1)

VDD = 3.3 V, TA = 25°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
PSRRSpurs induced by 50-mV power supply ripple(2)(3) at 156.25-MHz output, all output typesSine wave at 50 kHz–60dBc
Sine wave at 100 kHz–60
Sine wave at 500 kHz–60
Sine wave at 1 MHz–60
Refer to Parameter Measurement Information for relevant test conditions.
Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin
DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz.

PLL Clock Output Jitter Characteristics(1)(3)

VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
RJRMS phase jitter(2)
(12 kHz – 20 MHz)
fOUT ≥ 100 MHz, all output types150250fs RMS
Refer to Parameter Measurement Information for relevant test conditions.
Ensured by characterization.
Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).

Additional Reliability and Qualification

PARAMETERCONDITION / TEST METHOD
Mechanical ShockMIL-STD-202, Method 213
Mechanical VibrationMIL-STD-202, Method 204
Moisture Sensitivity LevelJ-STD-020, MSL3