LMK04828 超低抖动合成器和抖动消除器 | 德州仪器 TI.com.cn

LMK04828 (正在供货) 超低抖动合成器和抖动消除器

 

描述

The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems.

The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK0482x family ideal for providing flexible high performance clocking trees.

特性

  • JEDEC JESD204B Support
  • Ultra-Low RMS Jitter
    • 88 fs RMS Jitter (12 kHz to 20 MHz)
    • 91 fs RMS Jitter (100 Hz to 20 MHz)
    • –162.5 dBc/Hz Noise Floor at 245.76 MHz
  • Up to 14 Differential Device Clocks from PLL2
    • Up to 7 SYSREF Clocks
    • Maximum Clock Output Frequency 3.1 GHz
    • LVPECL, LVDS, HSDS, LCPECL
      Programmable Outputs from PLL2
  • Up to 1 Buffered VCXO/Crystal Output from PLL1
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Up to 3 Redundant Input Clocks
      • Automatic and Manual Switch-Over Modes
      • Hitless Switching and LOS
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover mode when Input Clocks are Lost
  • PLL2
    • Normalized [1 Hz] PLL Noise Floor of
      –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Two Integrated Low-Noise VCOs
  • 50% Duty Cycle Output Divides, 1 to 32
    (even and odd)
  • Precision Digital Delay, Dynamically Adjustable
  • 25 ps Step Analog Delay
  • Multi-mode: Dual PLL, single PLL, and Clock
    Distribution
  • Industrial Temperature Range: –40 to 85°C
  • Supports 105°C PCB Temperature (Measured at Thermal Pad)
  • 3.15-V to 3.45-V Operation
  • Package: 64-pin QFN (9.0 × 9.0 × 0.8 mm)

Design with LMK04828

Recommend Input Frequency Output Frequencies
 MHz
Input Frequency  MHz
 MHz  MHz

参数

与其它产品相比 单回路 PLL 邮件 下载到电子表格中
Part number 立即下单 Number of outputs Output type Output frequency (Min) (MHz) Output frequency (Max) (MHz) Number of Inputs Input type Supply voltage (Min) (V) Divider ratio Supply voltage (Max) (V) Features Operating temperature range (C) Rating
LMK04828 立即下单 15     HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.289     3080     3     CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
3.15     DevCLK 1 to 32
SYSREF 8 to 8191    
3.45     105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
-40 to 85     Catalog    
LMK04228 立即下单 15     LVDS
LVPECL
LVCMOS    
    3       3.15       3.45     JEDEC JESD204B Support
Dual PLL Architecture
Automatic and Manual Switch-Over Modes
Hitless Switching and LOS
Holdover Mode
OSCin Frequency Doubler
Multi-Mode Clock Distribution    
-40 to 85     Catalog    
LMK04616 立即下单 16     HCSL
HSDS
LVDS
LVPECL    
0.03     2000     4     CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
1.7     1 to 65535     3.465     105C PCB temp
Holdover mode
JESD204B SYSREF
JESD204B SYSREF Generation
Jitter Cleaner/Clock Generator/Clock Distribution
Integrated LDOs
Integrated Loop Filters
Low Power Design
Manual and automatic switching between inputs
Semi-Digital PLL
SPI    
-40 to 85     Catalog    
LMK04808 立即下单 14     LVCMOS
LVDS
LVPECL    
0.22     3072     2     CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
3.15     1 to 1045     3.45     uWire
SPI
Holdover mode
Manual/auto switch
Int. xtal oscillator    
-40 to 85     Catalog    
LMK04821 立即下单 15     HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.045     2075     3     CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
3.15     DevCLK 1 to 32
SYSREF 8 to 8191
VCO1Div 2 to 8    
3.45     105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
-40 to 85     Catalog    
LMK04826 立即下单 15     HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.225     2505     3     CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
3.15     DevCLK 1 to 32
SYSREF 8 to 8191    
3.45     105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
-40 to 85     Catalog    
LMK04832 立即下单 14     CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.305     3250     3       3.15       3.45     Holdover mode
JESD204B SYSREF Generation
Manual/auto switch
SPI    
-40 to 85