SNVS293F December   2004  – August 2016 LM5025A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Voltage Start-Up Regulator
      2. 7.3.2  Line Undervoltage Detector
      3. 7.3.3  PWM Outputs
      4. 7.3.4  Compound Gate Drivers
      5. 7.3.5  PWM Comparator
      6. 7.3.6  Volt Second Clamp
      7. 7.3.7  Current Limit
      8. 7.3.8  Oscillator and Sync Capability
      9. 7.3.9  Feed-Forward Ramp
      10. 7.3.10 Soft Start
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Oscillator
        2. 8.2.2.2 Soft-Start Ramp Time and Hiccup Interval
        3. 8.2.2.3 Feedforward Ramp and Maximum On-Time Clamp
        4. 8.2.2.4 Dead Times
      3. 8.2.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Protection
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VIN to GND –0.3 105 V
VCC to GND –0.3 16 V
CS1, CS2 to GND –0.3 1 V
All other inputs to GND –0.3 7 V
Junction temperature, TJ 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM)(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN voltage 13 90 V
External voltage applied to VCC 8 15 V
Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) LM5025A UNIT
PW (TSSOP) NHQ (WSON)
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 98.7 30 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.8 25.9 °C/W
RθJB Junction-to-board thermal resistance 44.3 9.3 °C/W
ψJT Junction-to-top characterization parameter 1.2 0.2 °C/W
ψJB Junction-to-board characterization parameter 43.6 9.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 2.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Typical limits are for TJ = 25°C, and minimum and maximum limits apply over the operating junction temperature range (–40°C to 125°C). VIN = 48 V, VCC = 10 V, RT = 31.3 kΩ, RSET = 27.4 kΩ) unless otherwise stated (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
START-UP REGULATOR
VCC Reg VCC regulation No load TJ = 25°C 7.6 V
TJ = Tlow to Thigh 7.3 7.9
VCC current limit  See (2) TJ = 25°C 25 mA
TJ = Tlow to Thigh 20
I-VIN Start-up regulator leakage (external Vcc Supply) VIN = 100 V TJ = 25°C 165 µA
TJ = Tlow to Thigh 500
VCC SUPPLY
VCC undervoltage lockout voltage (positive going Vcc) TJ = 25°C VCC Reg - 120 mV V
TJ = Tlow to Thigh VCC Reg -
220 mV
VCC undervoltage hysteresis TJ = 25°C 1.5 V
TJ = Tlow to Thigh 1 2
VCC supply current (ICC) Cgate = 0 TJ = Tlow to Thigh 4.2 mA
REFERENCE SUPPLY
VREF Ref voltage IREF = 0 mA TJ = 25°C 5 V
TJ = Tlow to Thigh 4.85 5.15
Ref voltage regulation IREF = 0 to 10mA TJ = 25°C 25 mV
TJ = Tlow to Thigh 50
Ref current limit TJ = 25°C 20 mA
TJ = Tlow to Thigh 10
CURRENT LIMIT
CS1 Prop CS1 delay to output CS1 Step from 0 to 0.6 V,
Time to onset of OUT Transition (90%),
Cgate = 0		 40 ns
CS2 Prop CS2 delay to output CS2 Step from 0 to 0.6 V,
Time to onset of OUT Transition (90%),
Cgate = 0		 50 ns
Cycle by cycle threshold voltage (CS1) TJ = 25°C 0.5 V
over full operating junction temperature 0.45 0.55
Cycle skip threshold voltage (CS2) Resets SS capacitor; auto restart TJ = 25°C 0.5 V
TJ = Tlow to Thigh 0.45 0.55
Leading edge blanking time (CS1) 50 ns
CS1 sink impedance (clocked) CS1 = 0.4 V TJ = 25°C 30 Ω
TJ = Tlow to Thigh 50
CS1 sink impedance (post fault discharge) CS1 = 0.6 V TJ = 25°C 15 Ω
TJ = Tlow to Thigh 30
CS2 sink impedance (post fault discharge) CS2 = 0.6 V TJ = 25°C 55 Ω
TJ = Tlow to Thigh 95
CS1 and CS2 leakage current CS = CS Threshold – 100 mV TJ = Tlow to Thigh 1 µA
SOFT-START
Soft-start current source normal TJ = 25°C 22 µA
over full operating junction temperature 17 27
Soft-start current source following a CS2 event TJ = 25°C 1 µA
over full operating junction temperature 0.5 1.5
OSCILLATOR
Frequency1 TA = 25°C, 180 200 220 kHz
TJ = Tlow to Thigh 175 225
Frequency2 RT = 10.4 kΩ TA = 25°C, 580 kHz
TJ = Tlow to Thigh 510 650
Sync threshold 2 V
Min sync pulse width TJ = Tlow to Thigh 100 ns
Sync frequency range TJ = Tlow to Thigh 160 kHz
PWM COMPARATOR
Delay to output COMP step 5 V to 0 V,
Time to onset of OUT_A transition low		 40 ns
Duty cycle range TJ = Tlow to Thigh 0% 80%
COMP to PWM offset TA = 25°C, 1 V
TJ = Tlow to Thigh 0.7 1.3
COMP open-circuit voltage TJ = Tlow to Thigh 4.3 5.9 V
COMP short-circuit current COMP = 0 V TA = 25°C, 1 mA
TJ = Tlow to Thigh 0.6 1.4
VOLT × SECOND CLAMP
Ramp clamp level Delta RAMP measured from onset of OUT_A to Ramp peak,
COMP = 5 V		 TA = 25°C, 2.5 V
TJ = Tlow to Thigh 2.4 2.6
UVLO SHUTDOWN
Undervoltage shutdown threshold TA = 25°C, 2.5 V
TJ = Tlow to Thigh 2.44 2.56
Undervoltage shutdown hysteresis TA = 25°C, 20 µA
TJ = Tlow to Thigh 16 24
OUTPUT SECTION
OUT_A high saturation MOS device at
Iout = –10 mA		 TA = 25°C, 5 Ω
TJ = Tlow to Thigh 10
OUTPUT_A peak current sink Bipolar Device at Vcc/2 3 A
OUT_A low saturation MOS device at
Iout = 10 mA		 TA = 25°C, 6 Ω
TJ = Tlow to Thigh 9
OUTPUT_A rise time Cgate = 2.2 nF 20 ns
OUTPUT_A fall time Cgate = 2.2 nF 15 ns
OUT_B high saturation MOS device at
Iout = –10 mA		 TA = 25°C, 10 Ω
TJ = Tlow to Thigh 20
OUTPUT_B peak current sink Bipolar device at Vcc/2 1 A
OUT_B low saturation MOS device at
Iout = 10 mA		 TA = 25°C, 12 Ω
TJ = Tlow to Thigh 18
OUTPUT_B rise time Cgate = 1 nF 20 ns
OUTPUT_B fall time Cgate = 1 nF 15 ns
OUTPUT TIMING CONTROL
Overlap time RSET = 38 kΩ connected to GND,
50% to 50% transitions		 TA = 25°C, 105 ns
TJ = Tlow to Thigh 75 135
Dead time RSET = 29.5 kΩ connected to REF,
50% to 50% transitions		 TA = 25°C, 105 ns
TJ = Tlow to Thigh 75 135
THERMAL SHUTDOWN
TSD Thermal shutdown threshold 165 °C
Thermal shutdown hysteresis 25 °C
(1) All electrical characteristics having room temperature limits are tested during production with TA = TJ = 25°C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) Device thermal limitations may limit usable range.

6.6 Typical Characteristics

LM5025A 20107403.gif
Figure 1. VCC Regulator Start-Up Characteristics, VCC vs VIN
LM5025A 20107405.gif
Figure 3. VREF vs IREF
LM5025A 20107407.gif
Figure 5. Overlap Time vs RSET
LM5025A 20107409.gif
Figure 7. Dead Time vs RSET
LM5025A 20107411.gif
Figure 9. SS Pin Current vs Temperature
LM5025A 20107404.gif
Figure 2. VCC vs ICC
LM5025A 20107406.png
Figure 4. Oscillator Frequency vs RT
LM5025A 20107408.gif
RSET = 38 K
Figure 6. Overlap Time vs Temperature
LM5025A 20107410.gif
RSET = 29.5 K
Figure 8. Dead Time vs Temperature